View W79E825ASN_6630218.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w79e825/824/823/822/821 data sheet 8-bit microcontroller publication release date: may 03, 2006 - 1 - revision a2 table of contents- 1. general des cription ......................................................................................................... 4 2. features ....................................................................................................................... .......... 4 3. parts informat ion list ..................................................................................................... 6 3.1 lead free (rohs) parts informati on list ......................................................................... 6 4. pin config urati on .............................................................................................................. .7 5. pin descri ption................................................................................................................ ..... 9 6. block di agram .................................................................................................................. .. 10 7. functional des cription ................................................................................................. 11 7.1 on-chip flas h eprom ................................................................................................ 11 7.2 i/o ports...................................................................................................................... .. 11 7.3 serial i/o ..................................................................................................................... .. 11 7.4 timers ......................................................................................................................... .. 11 7.5 interr upts..................................................................................................................... .. 11 7.6 data poin ters ................................................................................................................ 12 7.7 architec ture................................................................................................................... 12 7.8 power m anagement ...................................................................................................... 13 8. memory orga nizati on ..................................................................................................... 14 9. special function registers ......................................................................................... 19 10. instruct ion.................................................................................................................... ...... 48 10.1 instruction timing................................................................................................ 48 11. power mana gement .......................................................................................................... 52 11.1 idle mode ...................................................................................................................... 52 11.2 power down mode ....................................................................................................... 52 12. reset condi tions............................................................................................................... 53 12.1 external reset .............................................................................................................. 53 12.2 power-on rese t (por) ................................................................................................ 53 12.3 watchdog timer reset ................................................................................................. 53 12.4 reset state ................................................................................................................... 5 3 13. interrup ts ..................................................................................................................... ...... 56 13.1 interrupt s ources .......................................................................................................... 56 13.2 priority level structure ................................................................................................. 57 13.3 interrupt res ponse ti me .............................................................................................. 60 13.4 interrupt inputs.............................................................................................................. 6 0
w79e825/824/823a/822a/821a data sheet - 2 - 14. programmable time rs/count ers ............................................................................... 62 14.1 timer/counter s 0 & 1 ............................................................................................ 62 14.2 time-base se lection..................................................................................................... 62 14.3 mode 0 ........................................................................................................................ 6 2 14.4 mode 1 ........................................................................................................................ 6 3 14.5 mode 2 ........................................................................................................................ 6 4 14.6 mode 3 ........................................................................................................................ 6 4 15. nvm me mory ..................................................................................................................... .... 66 16. watchdog timer................................................................................................................. 69 16.1 watchdog co ntrol.............................................................................................. 70 16.2 clock control of watc hdog ................................................................................. 71 17. serial port (uar t) ............................................................................................................. 72 17.1 mode 0 ........................................................................................................................ 7 2 17.2 mode 1 ........................................................................................................................ 7 3 17.3 mode 2 ........................................................................................................................ 7 5 17.4 mode 3 ........................................................................................................................ 7 6 17.5 framing error detection ............................................................................................... 77 17.6 multiprocessor co mmunicati ons .................................................................................. 77 18. timed access pr otection .............................................................................................. 79 19. keyboard interrup t (kbi) ............................................................................................... 81 20. analog compar ators ...................................................................................................... 82 21. i/o port conf iguration ................................................................................................... 83 21.1 quasi-bidirectional out put configur ation ..................................................................... 83 21.2 open drain output configurat ion ................................................................................. 84 21.3 push-pull output configurat ion .................................................................................... 85 21.4 input only conf iguratio n ............................................................................................... 85 22. oscilla tor ..................................................................................................................... ...... 86 22.1 on-chip rc oscilla tor opti on ...................................................................................... 86 22.2 external clock input op tion .......................................................................................... 86 22.3 cpu clock rate select ................................................................................................. 87 23. power monitoring functio n ........................................................................................ 87 23.1 power on detect .......................................................................................................... 87 23.2 brownout de tect ........................................................................................................... 87 24. pulse width modulated outputs (pwm) ................................................................... 88 25. analog-to-digital conver ter ...................................................................................... 96 25.1 adc resolution and analog s upply:............................................................................ 97 26. i2c serial co ntrol ............................................................................................................ 9 9
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 3 - revision a2 26.1 sio1 port ...................................................................................................................... 99 26.2 the i2c control register s: ........................................................................................... 99 26.3 operating modes of i2c.............................................................................................. 103 27. icp(in-circuit program ) flash pr ogram ................................................................ 109 28. config bits .................................................................................................................... ..... 110 28.1 config 1 .................................................................................................................... 110 28.2 config 2 .................................................................................................................... 111 29. the on-chip debugger with jtag inte rface ......................................................... 113 30. absolute maximu m rating s ......................................................................................... 113 31. dc electrical cha racteris tics ................................................................................ 114 31.1 the adc converter dc electr ical charact eristi cs ................................... 115 31.2 the comparator electric al character istics ........................................ 116 32. ac electrical cha racteris tics................................................................................. 116 33. external clock cha racteris tics ............................................................................ 116 34. ac specific ation............................................................................................................... 117 35. typical applicat ion circui ts ...................................................................................... 117 36. package dime nsions ....................................................................................................... 118 36.1 20-pin so.................................................................................................................... 11 8 36.2 20-pin di p ................................................................................................................... 11 9 36.3 24-pin so.................................................................................................................... 12 0 37. revision hi story .............................................................................................................. 1 21
w79e825/824/823a/822a/821a data sheet - 4 - 1. general description the w79e82x series are an 8-bit turbo 51 micr ocontroller which has an in-system programmable flash eprom which flash eprom can program by icp (in circuit program) or by writer. the instruction set of the w79e82x serial are fully compatible with the standard 8052. the w79e82x series contain a 16k/8k/4k/2k/1k bytes of main flash eprom; a 256/128 bytes of ram; 256/128 bytes nvm data flash eprom; two 8-bit bi-direc tional, one 2-bit bi-directional and bit-addressable i/o ports; two 16-bit timer/counters; 4- channel multiplexed 10-bit a/d convert; 4/2 -channel 10-bit pwm; two serial ports that include a i2c and an enhanced full duplex serial port. these peripherals are supported by 13 sources four-level interrupt c apability. to facilitate programming and verification, the flash eprom inside the w79e82x series allo w the program memory to be programmed and read electronically. once the code is confirmed, the us er can protect the code for security. the w79e82x series also support the in-circuit emulation (ice ) function and a jtag interface to the development tool for debugging. 2. features ? fully static design 8-bit turbo 51 cmos micr ocontroller up to 20mhz when vdd=4.5v to 5.5v, 12mhz when vdd=2.7v to 5.5v ? 16k/8k/4k/2k/1k bytes of in-system-programmabl e flash eprom (ap flash eprom) ? 256/128 bytes of on-chip ram ? 256/128 bytes nvm data flash eprom for custom er data storage used and 10k writer cycles ? instruction-set compatible with msc-51 ? on-chip debug function with jtag interface to development tool ? two 8-bit bi-directional and one 2-bit bi-directional ports ? two 16-bit timer/counters ? 13 interrupts source with four levels of priority ? one enhanced full duplex serial port with frami ng error detection and automatic address recognition ? the 4 outputs mode and ttl/schmitt trigger selectable port ? programmable watchdog timer ? four/two -channel 10-bit pwm (pulse width modulator) ? four-channel multiplexed with 10-bits a/d convert ? one i2c communication port (master / slave) ? eight keypad interrupt inputs ? two analog comparators ? configurable on-chip oscillator ? led drive capability (20ma) on all port pins ? low voltage detect interrupt and reset ? packages: ? dip 20: w79e825adn
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 5 - revision a2 ? sop 20: W79E825ASN ? dip 20: w79e824adn ? sop 20: w79e824asn ? dip 20: w79e823adn ? sop 20: w79e823asn ? dip 20: w79e822adn ? sop 20: w79e822asn ? dip 20: w79e821adn ? sop 20: w79e821asn ? lead free (rohs) dip 20: w79e825adg ? lead free (rohs) sop 20: w79e825asg ? lead free (rohs) dip 20: w79e824adg ? lead free (rohs) sop 20: w79e824asg ? lead free (rohs) dip 20: w79e823adg ? lead free (rohs) sop 20: w79e823asg ? lead free (rohs) dip 20: w79e822adg ? lead free (rohs) sop 20: w79e822asg ? lead free (rohs) dip 20: w79e821adg ? lead free (rohs) sop 20: w79e821asg
w79e825/824/823a/822a/821a data sheet - 6 - 3. parts information list part no. eprom flash size ram nvm flash eprom adc pwm package remark w79e825adn 16kb 256b 256b 4x 10bit 4x10bit dip-20 pin W79E825ASN 16kb 256b 256b 4x10bit 4x10bit sop-20 pin w79e824adn 8kb 256b 256b 4x 10bit 4x10bit dip-20 pin w79e824asn 8kb 256b 256b 4x10bit 4x10bit sop-20 pin w79e823adn 4kb 128b 128b 4x 10bit 2x10bit dip-20 pin w79e823asn 4kb 128b 128b 4x10bit 2x10bit sop-20 pin w79e822adn 2kb 128b 128b 4x 10bit 2x10bit dip-20 pin w79e822asn 2kb 128b 128b 4x10bit 2x10bit sop-20 pin w79e821adn 1kb 128b 128b 4x 10bit 2x10bit dip-20 pin w79e821asn 1kb 128b 128b 4x10bit 2x10bit sop-20 pin 3.1 lead free (rohs) parts information list part no. eprom flash size ram nvm flash eprom adc pwm package remark w79e825adg 16kb 256b 256b 4x 10bit 4x10bit dip-20 pin w79e825asg 16kb 256b 256b 4x10bit 4x10bit sop-20 pin w79e824adg 8kb 256b 256b 4x 10bit 4x10bit dip-20 pin w79e824asg 8kb 256b 256b 4x10bit 4x10bit sop-20 pin w79e823adg 4kb 128b 128b 4x 10bit 2x10bit dip-20 pin w79e823asg 4kb 128b 128b 4x10bit 2x10bit sop-20 pin w79e822adg 2kb 128b 128b 4x 10bit 2x10bit dip-20 pin w79e822asg 2kb 128b 128b 4x10bit 2x10bit sop-20 pin w79e821adg 1kb 128b 128b 4x 10bit 2x10bit dip-20 pin w79e821asg 1kb 128b 128b 4x10bit 2x10bit sop-20 pin
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 7 - revision a2 4. pin configuration 1 2 20 19 18 17 16 15 14 13 12 11 3 4 5 6 7 8 9 10 pwm3/cmp2/p0.0 pwm2/p1.7 pwm1/p1.6 rst/p1.5 vss xtal1/p2.1 xtal2/clkout/p2.0 int1/p1.4 sda/int0/p1.3 scl/t0/p1.2 p0.1/cin2b/pwm0 p0.2/cin2a/brake p0.3/cin1b/ad0 p0.4/cin1a/ad1 p0.5/cmpref/ad2 vdd p0.6/cmp1/ad3 p0.7/t1 p1.0/txd p1.1/rxd 20 pin dip 1 2 20 19 18 17 16 15 14 13 12 11 3 4 5 6 7 8 9 10 pwm3/cmp2/p0.0 pwm2/p1.7 pwm1/p1.6 rst/p1.5 vss xtal1/p2.1 xtal2/clkout/p2.0 int1/p1.4 sda/int0/p1.3 scl/t0/p1.2 p0.1/cin2b/pwm0 p0.2/cin2a/brake p0.3/cin1b/ad0 p0.4/cin1a/ad1 p0.5/cmpref/ad2 vdd p0.6/cmp1/ad3 p0.7/t1 p1.0/txd p1.1/rxd 20 pin sop w79e825/w79e824 pin configuration
w79e825/824/823a/822a/821a data sheet - 8 - 1 2 20 19 18 17 16 15 14 13 12 11 3 4 5 6 7 8 9 10 cmp2/p0.0 p1.7 pwm1/p1.6 rst/p1.5 vss xtal1/p2.1 xtal2/clkout/p2.0 int1/p1.4 sda/int0/p1.3 scl/t0/p1.2 p0.1/cin2b/pwm0 p0.2/cin2a/brake p0.3/cin1b/ad0 p0.4/cin1a/ad1 p0.5/cmpref/ad2 vdd p0.6/cmp1/ad3 p0.7/t1 p1.0/txd p1.1/rxd 20 pin dip 1 2 20 19 18 17 16 15 14 13 12 11 3 4 5 6 7 8 9 10 cmp2/p0.0 p1.7 pwm1/p1.6 rst/p1.5 vss xtal1/p2.1 xtal2/clkout/p2.0 int1/p1.4 sda/int0/p1.3 scl/t0/p1.2 p0.1/cin2b/pwm0 p0.2/cin2a/brake p0.3/cin1b/ad0 p0.4/cin1a/ad1 p0.5/cmpref/ad2 vdd p0.6/cmp1/ad3 p0.7/t1 p1.0/txd p1.1/rxd 20 pin sop w79e823/w79e822/w79e82 1 pin configuration
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 9 - revision a2 5. pin description symbol type descriptions st r (p1.5) i reset: a low on this pin for two machine cycles while the oscillator is running resets the device. xtal1(p2.1) i/o crystal1: this is the crystal oscilla tor input. this pin may be driven by an external clock or configurable i/o pin. xtal2(p2.0) i/o crystal2: this is the crystal oscillato r output. it is the inversion of xtal1 or configurable i/o pin. vss p ground: ground potential vdd p power: supply: supply voltage for operation. p0.0 ? p0.7 i/o port 0: port 0 is four mode output pin and two mode input. the p0.3~p0.6 are 4-channel input ports (adc0-adc3) for adc used. p1.0 ? p1.7 i/o port 1: port 1 is four mode output pin and two mode input. the p1.2(scl) and p1.3(sda) is only open drain circuit, and p1.5 only input pin. * type: p: power, i: input, o: output, i/o: bi-directi onal, h: pull-high, l: pull-low, d: open-drain .
w79e825/824/823a/822a/821a data sheet - 10 - 6. block diagram alu stack pointer psw t1 register t2 register acc b instruction decoder & sequencer bus & lock controller dptr timer reg. pc dptr1 port 0 latch port 0 incrementor flash eprom port 2 latch port 2 power control & power monitor sfr & ram address 256 bytes ram & sfr timer 0 timer 1 interrupt uart port 1 latch port 1 oscillator xtal1 xtal2 watchdog timer reset block rst vcc gnd p2.0 | p2.1 p0.0 | p0.7 p1.0 | p1.7 watchdog rc oscillator comparator i2c pwm kbi on-chip rc oscillator adc
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 11 - revision a2 7. functional description the w79e82x series architecture consist of a 4t 8051 core controller surrounded by various registers, 16k/8k/4k/2k/1k bytes flash eprom, 256/128 bytes of ram, 256/128 bytes nvm data flash eprom, three general purpose i/o ports, two timer/counters, one serial port, one i2c serial i/o, 4/2 channel pwm with 10-bit counter, 4-channel mu ltiplexed with 10-bit adc analog input, flash eprom program by writer and icp. 7.1 on-chip flash eprom the w79e82x series include one 16k/8k/4k/2k/1k bytes of main flash eprom for application program when operating the in-circuit programming features by the flash eprom itself which need writer or icp program board to program the flash eprom. this icp(in-circu it programming) feature makes the job easy and efficient in which the applic ation needs to update firmware frequently. in some applications, the in-circuit programming feature make s it possible that the end-user is able to easily update the system firmware by them selves without opening the chassis. 7.2 i/o ports the w79e82x series have two 8-bit and one 2-bit por t, up to 18 i/o pins using on-chip oscillator & reset options. all ports can be used as four out puts mode when it may set by pxm1.y and pxm2.y registers, it has strong pull-ups and pull-downs, and does not need any external pull-ups. otherwise it can be used as general i/o port as open drain circui t. all ports can be used bi-directional and these are as i/o ports. these ports are not true i/o, but rather are pseudo- i/o ports. this is because these ports have strong pull-dow ns and weak pull-ups. 7.3 serial i/o the w79e82x series have one serial port that is functi onally similar to the serial port of the original 8032 family. however the serial port on the w79e82x series can operate in different modes in order to obtain timing similarity as well. the serial port has the enhanced features of automatic address recognition and frame error detection. 7.4 timers the w79e82x series have two 16-bit timers that ar e functionally and similar to the timers of the 8052 family. when used as timers, they are set 12 or 4 clocks per count that emul ates the timing of the original 8052. 7.5 interrupts the interrupt structure in the w79e82x series are slightly different from that of the standard 8052. due to the presence of additional features and per ipherals, the number of interrupt sources and vectors has been increased.
w79e825/824/823a/822a/821a data sheet - 12 - 7.6 data pointers the data pointer of w79e82x series same as 8052 that has dual 16-bit data pointers (dptr) by setting dps of auxr1.0, power management like t he standard 8052, the w79e82x series also have the idle and power down modes of operation. in the idle mode, the clo ck to the cpu is stopped while the timers, serial ports and interrupt lock c ontinue to operate. in the power down mode, all clocks are stopped and the chip operation is comp letely stopped. this is the lowest power consumption state. the figure of dual dprt is as below diagram. dptr dptr dps auxr1.0 dps=0 dps=1 7.7 architecture the w79e82x series are based on the standard 8052 devic e. it is built around an 8-bit alu that uses internal registers for temporary storage and contro l of the peripheral devices. it can execute the standard 8052 instruction set. 7.7.1 alu the alu is the heart of the w79e82x series. it is re sponsible for the arithmetic and logical functions. it is also used in decision making, in case of jump instructions, and is also used in calculating jump addresses. the user cannot directly use the alu, but the instruction decoder reads the op-code, decodes it, and sequences the data through the alu and its associated registers to generate the required result. the alu mainly uses the acc which is a special function register (sfr) on the chip. another sfr, namely b register is also used in multiply and divide instructions. the alu generates several status signals which are stored in t he program status word register (psw). 7.7.2 accumulator the accumulator (acc) is the primary register us ed in arithmetic, logical and data transfer operations in the w79e82x series. since the accumulator is di rectly accessible by the cpu, most of the high speed instructions make use of the acc as one argument. 7.7.3 b register this is an 8-bit register that is used as the se cond argument in the mul and div instructions. for all other instructions it can be used si mply as a general purpose register. 7.7.4 program status word: this is an 8-bit sfr that is used to store the stat us bits of the alu. it holds the carry flag, the auxiliary carry flag, general purpose flags, the register bank select, the overflow flag, and the parity flag.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 13 - revision a2 7.7.5 scratch-pad ram the w79e82x series have a 256/128 bytes on-chip scratch-pad ram. these can be used by the user for temporary storage during program execution. a ce rtain section of this ram is bit addressable, and can be directly addressed for this purpose. 7.7.6 stack pointer the w79e82x series have an 8-bit stack pointer whic h points to the top of the stack. this stack resides in the scratch pad ram in the w79e82x seri al. hence the size of t he stack is limited by the size of this ram. 7.8 power management like the standard 8051/52, the w79e201 has idle and power down modes of operation. in power down mode, all of the peripheral clocks are stopped, and chip operation stops completely. this mode consumes the least amount of power.
w79e825/824/823a/822a/821a data sheet - 14 - 8. memory organization the w79e82x series separate the memory into tw o separate sections, the program memory and the data memory. the program memory is used to stor e the instruction op-codes, while the data memory is used to store data or for memory mapped devices. program memory the program memory on the w79e82x series can be up to 16k/8k/4k/2k/1k bytes long. all instructions are fetched for execution from this me mory area. the movc instruction can also access this memory region. data memory the nvm data memory of flash eprom on the w79e82x series can be up to 256/128 bytes long. the w79e82x series read the c ontent of data memory by usi ng ?movc @a+dptr?. the w79e82x series only read access config registers by the mo vc instruction. to wr ite data is by nvmaddr, nvmdat and nvmcon sfr?s registers. 0000h external data memory space on-chip code memory space 0000h 16k/8k bytes on-chip code memory unused code memory unused code memory config 1 3fffh 4000h ffffh ffffh page 0 64 bytes page 1 64 bytes page 2 64 bytes page 3 64 bytes fc00h fc3fh fc40h fc7fh fc80h fcbfh fcc0h fcffh nvm data memory area fc00h config 2 fcffh 256 bytes nvm data memory unused data memory fbffh w79e825/w79e824 memory map
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 15 - revision a2 0000h external data memory space on-chip code memory space 0000h 4k/2k/1k bytes on-chip code memory unused code memory unused code memory 0fffh 1000h ffffh ffffh page 0 64 bytes page 1 64 bytes fc00h fc3fh fc40h fc7fh nvm data memory area fc00h fc7fh 128 bytes nvm data memory unused data memory config 1 config 2 w79e823/w79e822/w79e821 memory map register map as mentioned before the w79e82x series have separate program and data memory areas. the on- chip 256/128 bytes scratch pad ram is in addition to the external memory. there are also several special function registers (sfrs) which can be accessed by software. the sfrs can be accessed only by direct addressing, while the on-chip ram can be accessed by either direct or indirect addressing.
w79e825/824/823a/822a/821a data sheet - 16 - indirect ram addressing direct & indirect ram addressing sfr direct addressing only 00h 7fh 80h ffh ram and sfr data memory space w79e825/w79e824 ram and sfr memory map the w79e823, w79e822 and w79e821 ram and sf r memory map as below figure: unused indirect ram direct & indirect ram addressing sfr direct addressing only 00h 7fh 80h ffh ram and sfr data memory space w79e823/w79e822/w79e821 ram and sfr memory map since the scratch-pad ram is only 256/128 bytes it can be used only when data contents are small. there are several other special purpose areas with in the scratch-pad ram. these are described as follows.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 17 - revision a2 bank 0 bank 1 bank 2 bank 3 03 02 01 00 04 05 06 07 0b 0a 09 08 0c 0d 0e 0f 13 12 11 10 14 15 16 17 1b 1a 19 18 1c 1d 1e 1f 23 22 21 20 24 25 26 27 2b 2a 29 28 2c 2d 2e 2f 33 32 31 30 34 35 36 37 3b 3a 39 38 3c 3d 3e 3f 43 42 41 40 44 45 46 47 4b 4a 49 48 4c 4d 4e 4f 53 52 51 50 54 55 56 57 5b 5a 59 58 5c 5d 5e 5f 63 62 61 60 64 65 66 67 6b 6a 69 68 6c 6d 6e 6f 73 72 71 70 74 75 76 77 7b 7a 79 78 7c 7d 7e 7f direct ram indirect ram 00h 07h 28h 08h 0fh 10h 17h 18h 1fh 20h 21h 22h 23h 24h 25h 26h 27h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 7fh 80h ffh working registers there are four sets of working registers, each cons isting of eight 8-bit registers. these are termed ads banks 0, 1, 2, and 3. individual registers within these banks can be directly accessed by separate instructions. these individual registers are named as r0, r1, r2, r3, r4, r5, r6 and r7. however, at one time the w79e82x series can work with only one particular bank. the bank selection is done by setting rs1-rs0 bits in the psw. the r0 and r1 registers are used to store the address for indirect accessing.
w79e825/824/823a/822a/821a data sheet - 18 - bit addressable locations the scratch-pad ram area from location 20h to 2fh is byte as well as bit addressable. this means that a bit in this area can be individually address ed. in addition some of the sfrs are also bit addressable. the instruction decoder is able to disti nguish a bit access from a byte access by the type of the instruction itself. in the sfr area, any existing sfr whose address ends in a 0 or 8 is bit addressable. stack the scratch-pad ram can be used for the stack. this area is selected by the stack pointer (sp), which stores the address of the t op of the stack. whenever a jump, call or interrupt is invoked the return address is placed on the stack. there is no re striction as to where the stack can begin in the ram. by default however, the stack pointer contai ns 07h at reset. the user can then change this to any value desired. the sp will point to the last used value. therefore, the sp will be incremented and then address saved onto the stack. conversely, while popping from t he stack the contents will be read first, then the sp is decreased.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 19 - revision a2 9. special function registers the w79e82x series uses special function regist ers (sfrs) to control and monitor peripherals and their modes. the sfrs reside in the register lo cations 80-ffh and are accessed by direct addressing only. some of the sfrs are bit addressable. this is very useful in cases where we wish to modify a particular bit without changing the others. the sf rs that are bit addressable are those whose addresses end in 0 or 8. the w79e82x series c ontain all the sfrs present in the standard 8052. however some additional sfrs are added. in some cases the unused bits in the original 8052, have been given new functions. the list of the sfrs is as follows. table 1 special function register location table f8 ip1 f0 b p0id ip1h e8 ie1 e0 acc adccon adch d8 wdcon pwmpl pwm0l pwm1l pwmcon1 (3) pwm2l (4) pwm3l (4) pwmcon2 (3) d0 psw pwmph pwm0h pwm1h pwm2h (4) pwm3h (4) pwmcon3 c8 nvmcon nvmdat c0 i2con i2addr nvmaddr ta b8 ip0 saden i2data i2status i2clk i2timer b0 p0m1 p0m2 p1m1 p1m2 p2m1 p2m2 ip0h a8 ie saddr cmp1 cmp2 a0 p2 kbi auxr1 98 scon sbuf 90 p1 divm 88 tcon tmod tl0 tl1 th0 th1 ckcon 80 p0 sp dpl dph pcon note: 1. the sfrs in the column wi th dark borders are bit-addressable 2. the table is condensed with eight loca tions per row. empty locations indicate that these are no registers at these addresses. when a bit or register is not implemented, it will read high. 3. the pwm2 and pwm 3 control bits of pwmc on1 and pwmcon2 sfr registers are reversed. 4. the w79e823, w79e822 and w79e821 without pwm2 l, pwm2h, pwm3l and pwm3h sfr registers.
w79e825/824/823a/822a/821a data sheet - 20 - port 0 bit: 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 mnemonic: p0 address: 80h port 0 is an open-drain bi-directional i/o port. stack pointer bit: 7 6 5 4 3 2 1 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 mnemonic: sp address: 81h the stack pointer stores the scratchpad ram addre ss where the stack begins. in other words, it always points to the top of the stack. data pointer low bit: 7 6 5 4 3 2 1 0 dpl.7 dpl.6 dpl.5 dpl.4 dpl.3 dpl.2 dpl.1 dpl.0 mnemonic: dpl address: 82h this is the low byte of the standard 8052 16-bit data pointer. data pointer high bit: 7 6 5 4 3 2 1 0 dph.7 dph.6 dph.5 dph.4 dph.3 dph.2 dph.1 dph.0 mnemonic: dph address: 83h this is the high byte of the standard 8052 16-bit data pointer. this is the high byte of the dptr 16-bit data pointer. power control bit: 7 6 5 4 3 2 1 0 smod smod0 bof por gf1 gf0 pd idl mnemonic: pcon address: 87h
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 21 - revision a2 bit name function 7 smod 1: this bit doubles the serial port baud rate in mode 1, 2, and 3. 6 smod0 0: framing error detection disable. scon .7 acts as per the standard 8052 function. 1: framing error detection enable, t hen and scon.7 indicates a frame error and acts as the fe flag. 5 bof 0: cleared by software. 1: set automatically when a brownout reset or interrupt has occurred. also set at power on. 4 por 0: cleared by software. 1: set automatically when a power-on reset has occurred. 3 gf1 general purpose user flags. 2 gf0 general purpose user flags. 1 pd 1: the cpu goes into the power down m ode. in this mode, all the clocks are stopped and program execution is frozen. 0 idl 1: the cpu goes into the idle mode. in this mode, the clocks cpu clock stopped, so program execution is frozen. but the clock to the serial, timer and interrupt blocks is not stopped, and these blo cks continue operating. timer control bit: 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 mnemonic: tcon address: 88h bit name function 7 tf1 timer 1 overflow flag: this bit is set when timer 1 overflows. it is cleared automatically when the program does a timer 1 interrupt se rvice routine. software can also set or clear this bit. 6 tr1 timer 1 run control: this bit is set or cl eared by software to turn timer/counter on or off. 5 tf0 timer 0 overflow flag: this bit is set when timer 0 overflows. it is cleared automatically when the program does a timer 0 interrupt se rvice routine. software can also set or clear this bit. 4 tr0 timer 0 run control: this bit is set or cl eared by software to turn timer/counter on or off. 3 ie1 interrupt 1 edge detect: set by har dware when an edge/level is detected on int1 . this bit is cleared by hardware when the service r outine is vectored to only if the interrupt was edge triggered. otherwise it follows the pin.
w79e825/824/823a/822a/821a data sheet - 22 - continued bit name function 2 it1 interrupt 1 type control: set/cleared by software to specify falling edge/ low level triggered external inputs. 1 ie0 interrupt 0 edge detect: set by har dware when an edge/level is detected on int0 . this bit is cleared by hardware when the service r outine is vectored to only if the interrupt was edge triggered. otherwise it follows the pin. 0 it0 interrupt 0 type control: set/cleared by software to specify falling edge/ low level triggered external inputs. timer mode control bit: 7 6 5 4 3 2 1 0 gate t c/ m1 m0 gate t c/ m1 m0 mnemonic: tmod address: 89h bit name function 7 gate gating control: when this bit is se t, timer/counter 1 is enabled only while int1 pin is high and tr1 control bit is set. when cleared, timer 1 is enabled whenever tr1 control bit is set. 6 t c/ timer or counter select: when cleared, the timer is incremented by internal clocks. when set, the timer counts high-to-low edges of the t1 pin. 5 m1 timer1 mode select bit1: see table below. 4 m0 timer1 mode select bit0: see table below. 3 gate gating control: when this bit is se t, timer/counter 0 is enabled only while int0 pin is high and tr0 control bit is set. when cleared, timer 0 is enabled whenever tr0 control bit is set. 2 t c/ timer or counter select: when cleared, the timer is incremented by internal clocks. when set, the timer counts high-to-low edges of the t0 pin. 1 m1 timer0 mode select bit1: see table below. 0 m0 timer0 mode select bit0: see table below.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 23 - revision a2 m1, m0: mode select bits: m1 m0 mode 0 0 mode 0: 8-bits with 5-bit prescale. 0 1 mode 1: 16-bits, no prescale. 1 0 mode 2: 8-bits with auto-reload from thx 1 1 mode 3: (timer 0) tl0 is an 8-bit timer/ counter controlled by the standard timer 0 control bits. th0 is a 8-bit timer only cont rolled by timer 1 control bits. (timer 1) timer/counter is stopped. timer 0 lsb bit: 7 6 5 4 3 2 1 0 tl0.7 tl0.6 tl0.5 tl0.4 tl0.3 tl0.2 tl0.1 tl0.0 mnemonic: tl0 address: 8ah tl0.7-0: timer 0 lsb timer 1 lsb bit: 7 6 5 4 3 2 1 0 tl1.7 tl1.6 tl1.5 tl1.4 tl1.3 tl1.2 tl1.1 tl1.0 mnemonic: tl1 address: 8bh tl1.7-0: timer 1 lsb timer 0 msb bit: 7 6 5 4 3 2 1 0 th0.7 th0.6 th0.5 th0.4 th0.3 th0.2 th0.1 th0.0 mnemonic: th0 address: 8ch th0.7-0: timer 0 msb timer 1 msb bit: 7 6 5 4 3 2 1 0 th1.7 th1.6 th1.5 th1.4 th1.3 th1.2 th1.1 th1.0 mnemonic: th1 address: 8dh th1.7-0: timer 1 msb
w79e825/824/823a/822a/821a data sheet - 24 - clock control bit: 7 6 5 4 3 2 1 0 - - - t1m t0m - - - mnemonic: ckcon address: 8eh bit name function 7~5 p1.7 reserved 4 t1m timer 1 clock select: 0: timer 1 uses a divide by 12 clocks. 1: timer 1 uses a divide by 4 clocks. 3 t0m timer 0 clock select: 0: timer 0 uses a divide by 12 clocks. 1: timer 0 uses a divide by 4 clocks. 2~0 p1.2 reserved port 1 bit: 7 6 5 4 3 2 1 0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 mnemonic: p1 address: 90h p1.7-0: general purpose input/output port. most instru ctions will read the port pins in case of a port read access, however in case of read-modify-write in structions, the port latch is read. these alternate functions are described below: bit name function 7 p1.7 pwm 2 pin 6 p1.6 pwm 1 pin 5 p1.5 rst pin or input pin by alternative 4 p1.4 int1 interrupt 3 p1.3 int0 interrupt or sda of i 2 c 2 p1.2 timer 0 or scl of i 2 c 1 p1.1 rxd of serial port 0 p1.0 txd of serial port divider clock bit: 7 6 5 4 3 2 1 0 divm.7 divm.6 divm.5 divm.4 divm.3 divm.2 divm.1 divm.0 mnemonic: divm address: 95h the divm register is clock divider of uc. refer oscillator chapter.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 25 - revision a2 serial port control bit: 7 6 5 4 3 2 1 0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri mnemonic: scon address: 98h bit name function 7 sm0/fe serial port mode select bit 0 or framing error flag: the smod0 bit in pcon sfr determines whether this bit ac ts as sm0 or as fe. the operation of sm0 is described below. when used as fe, this bit will be set to indicate an invalid stop bit. this bit must be manually cleared in software to clear the fe condition. 6 sm1 serial port mode bit 1: mode: sm0 sm1 description length baud rate 0 0 0 synchronous 8 4/12 tclk 1 0 1 asynchronous 10 variable 2 1 0 asynch ronous 11 64/32 tclk 3 1 1 asynchronous 11 variable 5 sm2 multiple processors communication. setting this bit to 1 enables the multiprocessor communication feature in mode 2 and 3. in mode 2 or 3, if sm2 is set to 1, then ri will not be activated if the received 9th data bit (r b8) is 0. in mode 1, if sm2 = 1, then ri will not be activated if a valid stop bit wa s not received. in mode 0, the sm2 bit controls the serial port clock. if set to 0, t hen the serial port runs at a divide by 12 clock of the oscillator. this gives compatibilit y with the standard 8052. when set to 1, the serial clock become divide by 4 of the o scillator clock. this results in faster synchronous serial communication. 4 ren receive enable: when set to 1 serial rec eption is enabled, otherwise reception is disabled. 3 tb8 this is the 9th bit to be transmitted in m odes 2 and 3. this bit is set and cleared by software as desired. 2 rb8 in modes 2 and 3 this is the received 9th dat a bit. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0 it has no function. 1 ti transmit interrupt flag: this flag is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in all other modes during serial transmission. this bit must be cleared by software. 0 ri receive interrupt flag: this flag is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bits time in the other modes during serial reception. however the restrictions of sm 2 apply to this bit. this bit can be cleared only by software.
w79e825/824/823a/822a/821a data sheet - 26 - serial data buffer bit: 7 6 5 4 3 2 1 0 sbuf.7 sbuf.6 sbuf.5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0 mnemonic: sbuf address: 99h bit name function 7~0 sbuf serial data on the serial port is read from or wr itten to this location. it actually consists of two separate internal 8-bit registers. one is the receive resister, and the other is the transmit buffer. any read access gets data fr om the receive data buffer, while write access is to the transmit data buffer. port 2 bit: 7 6 5 4 3 2 1 0 - - - - - - p2.1 p2.0 mnemonic: p2 address: a0h bit name function 7~2 - reserved 1 p2.1 xtal2 or clkout pin by alternative. 0 p2.0 xtal1 clock input pin. keyboard interrupt bit: 7 6 5 4 3 2 1 0 kbi.7 kbi.6 kbi.5 kbi.4 kbi.3 kbi.2 kbi.1 kbi.0 mnemonic: kbi address: a1h
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 27 - revision a2 keyboard interrupt enable. bit name function 7 kbi.7 1: enable p0.7 as a cause of a keyboard interrupt. 6 kbi.6 1: enable p0.6 as a cause of a keyboard interrupt. 5 kbi.5 1: enable p0.5 as a cause of a keyboard interrupt. 4 kbi.4 1: enable p0.4 as a cause of a keyboard interrupt. 3 kbi.3 1: enable p0.3 as a cause of a keyboard interrupt. 2 kbi.2 1: enable p0.2 as a cause of a keyboard interrupt. 1 kbi.1 1: enable p0.1 as a cause of a keyboard interrupt. 0 kbi.0 1: enable p0.0 as a cause of a keyboard interrupt. aux function register 1 bit: 7 6 5 4 3 2 1 0 kbf bod boi lpbov srst adcen 0 dps mnemonic: auxr1 address: a2h bit name function 7 kbf keyboard interrupt flag: 1: when any pin of port 0 that is enabled fo r the keyboard interrupt function goes low. must be cleared by software. 6 bod brown out disable: 0: enable brownout detect function. 1: disable brownout detect function and save power. 5 boi brown out interrupt: 0: disable brownout detect interrupt functi on and it will cause chip reset when bof is set. 1: this prevents brownout detection from causing a chip reset and allows the brownout detect function to be used as an interrupt. 4 lpbov low power brown out detect control: 0: when bod is enable, the brown out detec t is always turned on by normal run or power down mode. 1: when bod is enable, the 1/16 time will be turned on brown out detect circuit by power down mode. when uc is in power down mode, the bod will enable internal rc osc(2mhz~0.5mhz) 3 srst software reset: 1: reset the chip as if a hardware reset occurred. 2 adcen 0: disable adc circuit. 1: enable adc circuit. 1 0 reserved 0 dps dual data pointer select 0: to select dptr of standard 8051. 1: to select dptr1
w79e825/824/823a/822a/821a data sheet - 28 - interrupt enable bit: 7 6 5 4 3 2 1 0 ea eadc ebo es et1 ex1 et0 ex0 mnemonic: ie address: a8h bit name function 7 ea global enable. enable/disable all interrupts. 6 eadc enable adc interrupt. 5 ebo enable brown out interrupt. 4 es enable serial port interrupt. 3 et1 enable timer 1 interrupt. 2 ex1 enable external interrupt 1. 1 et0 enable timer 0 interrupt. 0 ex0 enable external interrupt 0. slave address bit: 7 6 5 4 3 2 1 0 saddr.7 saddr.6 saddr. 5 saddr.4 saddr.3 sa ddr.2 saddr.1 saddr.0 mnemonic: saddr address: a9h bit name function 7 saddr the saddr should be programmed to the given or broadcast address for serial port 0 to which the slave processor is designated. comparator 1 control register bit: 7 6 5 4 3 2 1 0 - - ce1 cp1 cn1 oe1 co1 cmf1 mnemonic: cmp1 address: ach
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 29 - revision a2 bit name function 7 - reserved 6 - reserved 5 ce1 comparator enable: 0: disable comparator. 1: enabled comparator. comparator output need wait stable 10 us after ce1 is first set. 4 cp1 comparator positive input select: 0: cin1a is selected as the positive comparator input. 1: cin1b is selected as the positive comparator input. 3 cn1 comparator negative input select: 0: the comparator reference pin cmpref is selected as the negative comparator input. 1: the internal comparator reference vr ef is selected as the negative comparator input. 2 oe1 output enable: 1: the comparator output is connected to the cmp1 pin if the comparator is enabled (ce1 = 1). this output is asynchronous to the cpu clock. 1 co1 comparator output: synchronized to the cpu clock to allo w reading by software. cleared when the comparator is disabled (ce1 = 0). 0 cmf1 comparator interrupt flag: this bit is set by hardware whenever the comparator output co1 changes state. this bit will cause a hardware interrupt if enabl ed and of sufficient priority. cleared by software and when the comparator is disabled (ce1 = 0). comparator 2 control register bit: 7 6 5 4 3 2 1 0 - - ce2 cp2 cn2 oe2 co2 cmf2 mnemonic: cmp2 address: adh
w79e825/824/823a/822a/821a data sheet - 30 - bit name function 7 - reserved 6 - reserved 5 ce2 comparator enable: 0: disable comparator. 1: enabled comparator. comparator output need wait stable 10 us after ce2 is first set. 4 cp2 comparator positive input select: 0: cin2a is selected as the positive comparator input. 1: cin2b is selected as the positive comparator input. 3 cn2 comparator negative input select: 0: the comparator reference pin cmpref is selected as the negative comparator input. 1: the internal comparator reference vref is selected as the negative comparator input. 2 oe2 output enable: 1: the comparator output is connected to the cmp2 pin if the comparator is enabled (ce2 = 1). this output is asynchronous to the cpu clock. 1 co2 comparator output: synchronized to the cpu clock to a llow reading by software. cleared when the comparator is disabled (ce2 = 0). 0 cmf2 comparator interrupt flag: this bit is set by hardware whenever the co mparator output co2 changes state. this bit will cause a hardware interrupt if enabled and of sufficient priority. cleared by software and when the comparator is disabled (ce2 = 0). port 0 output mode 1 bit: 7 6 5 4 3 2 1 0 p0m1.7 p0m1.6 p0m1.5 p0m1 .4 p0m1.3 p0m1.2 p0m1.1 p0m1.0 mnemonic: p0m1 address: b1h port 0 output mode 2 bit: 7 6 5 4 3 2 1 0 p0m2.7 p0m2.6 p0m2.5 p0m2 .4 p0m2.3 p0m2.2 p0m2.1 p0m2.0 mnemonic: p0m2 address: b2h
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 31 - revision a2 port 1 output mode 1 bit: 7 6 5 4 3 2 1 0 p1m1.7 p1m1.6 - p1m1.4 - - p1m1.1 p1m1.0 mnemonic: p1m1 address: b3h port 1 output mode 2 bit: 7 6 5 4 3 2 1 0 p1m2.7 p1m2.6 - p1m2.4 - - p1m2.1 p1m2.0 mnemonic: p1m2 address: b4h port 2 output mode 1 bit: 7 6 5 4 3 2 1 0 p2s p1s p0s enclk t1oe t0oe p2m1.1 p2m1.0 mnemonic: p2m1 address: b5h port 2 output mode 2 bit: 7 6 5 4 3 2 1 0 - - - - - - p2m2.1 p2m2.0 mnemonic: p2m2 address: b6h bit name function 7 p2s 1: enables schmitt trigger inputs on port 2. 6 p1s 1: enables schmitt trigger inputs on port 1. 5 p0s 1: enables schmitt trigger inputs on port 0. 4 enclk 1: to use the on-chip rc oscillator, a cl ock output is enabled on the xtal2 pin (p2.0). 3 t1oe 1: the p0.7 pin is toggled whenever ti mer 1 overflows. the output frequency is therefore one half of the timer 1 overflow rate. 2 t0oe 1: the p1.2 pin is toggled whenever ti mer 1 overflows. the output frequency is therefore one half of the timer 1 overflow rate. 1 p2m1.1 to control the output configuration of p2.1. 0 p2m1.0 to control the output configuration of p2.0.
w79e825/824/823a/822a/821a data sheet - 32 - port output configuration settings: pxm1.y pxm2.y port input/output mode 0 0 quasi-bidirectional 0 1 push-pull 1 0 input only (high impedance) 1 1 open drain interrupt high priority bit: 7 6 5 4 3 2 1 0 - padch pboh psh pt1h px1h pt0h px0h mnemonic: ip0h address: b7h bit name function 7 - this bit is un-implemented and will read high. 6 padch 1: to set interrupt high priority of adc is highest priority level. 5 pboh 1: to set interrupt high priority of br own out detector is highest priority level. 4 psh 1: to set interrupt high priority of serial port 0 is highest priority level. 3 pt1h 1: to set interrupt high priority of timer 1 is highest priority level. 2 px1h 1: to set interrupt high priority of ex ternal interrupt 1 is highest priority level. 1 pt0h 1: to set interrupt high priority of timer 0 is highest priority level. 0 px0h 1: to set interrupt high priority of ex ternal interrupt 0 is highest priority level. interrupt priority0 bit: 7 6 5 4 3 2 1 0 - padc pbo ps pt1 px1 pt0 px0 mnemonic: ip0 address: b8h bit name function 7 - this bit is un-implemented and will read high. 6 padc 1: to set interrupt priority of adc is higher priority level. 5 pbo 1: to set interrupt priority of brow n out detector is higher priority level. 4 ps 1: to set interrupt priority of se rial port 0 is higher priority level. 3 pt1 1: to set interrupt priority of timer 1 is higher priority level. 2 px1 1: to set interrupt priority of exte rnal interrupt 1 is higher priority level. 1 pt0 1: to set interrupt priority of timer 0 is higher priority level. 0 px0 1: to set interrupt priority of exte rnal interrupt 0 is higher priority level.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 33 - revision a2 slave address mask enable bit: 7 6 5 4 3 2 1 0 mnemonic: saden address: b9h bit name function 7~0 saden this register enables the automatic address recognition feature of the serial port 0. when a bit in the saden is set to 1, the same bit location in saddr will be compared with the incoming serial data. when saden is 0, then the bit becomes a "don't care" in the comparison. this register enables the automatic address recognition feature o f the serial port 0. when all the bits of saden are 0, interrupt will occur for any incoming address. i2c data register bit: 7 6 5 4 3 2 1 0 i2dat.7 i2dat.6 i2dat.5 i2dat.4 i2dat.3 i2dat.2 i2dat.1 i2dat.0 mnemonic: i2dat address: bch bit name function 0~7 i2dat the data register of i2c. i2c status register bit: 7 6 5 4 3 2 1 0 - - - mnemonic: i2status address: bdh bit name function 0~7 i2status the status register of i2c: the three least significant bits are always 0. the five most significant bits contain the status code. there are 23 possible status codes. when i2statuscontains f8h, no serial interrupt is requested. all other i2status values correspond to defined i2c states. when each of these stat es is entered, a status inte rrupt is requested (si = 1). a valid status code is present in i2stat us one machine cycle after si is set by hardware and is still present one machine cycl e after si has been reset by software. in addition, states 00h stands for a bus e rror. a bus error occurs when a start or stop condition is present at an illegal posit ion in the formation frame. example o f illegal position are during the serial trans fer of an address byte, a data byte or an acknowledge bit.
w79e825/824/823a/822a/821a data sheet - 34 - i2c baud rate control register bit: 7 6 5 4 3 2 1 0 i2clk.7 i2clk.6 i2clk.5 i2clk.4 i2clk.3 i2clk.2 i2clk.1 i2clk.0 mnemonic: i2clk address: beh bit name function 7~ 0 i2clk the i2c clock rate bits. i2c timer counter register bit: 7 6 5 4 3 2 1 0 - - - - - enti div4 tif mnemonic: i2timer address: bfh bit name function 7~3 - reserved. 2 enti enable i2c 14-bits timer counter: 0: disable 14-bits timer counter count. 1: enable 14-bits timer counter count. after enable it, the 14-bit counter will be cleared. if si flag of i2c is set, the counter can?t up count. 1 div4 i2c timer counter clock source divide function: 0: the 14-bits timer counter source clock is fosc clock. 1: the 14-bits timer counter source clock is divided by 4. 0 tif the i2c timer counter count flag: 0: the 14-bits timer counter is not overflow. 1: the 14-bits timer counter is overflow. before enable i2c timer(enti) the si must be cleared. if i2c interrupt is enabled then will executed i2c interrupt service routine. this bit clear by software. i2c control register bit: 7 6 5 4 3 2 1 0 - ens1 sta sto si aa - - mnemonic: i2con address: c0h
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 35 - revision a2 bit name function 7 - reserved. 6 ens1 enable i2c serial function. 5 sta the start flag of i2c. 4 sto the stop flag of i2c. 3 si the interrupt flag of i2c. 2 aa the assert acknowledge flag of i2c. 1 - reserved. 0 - reserved. i2c address register bit: 7 6 5 4 3 2 1 0 i2addr. 7 i2addr. 6 i2addr. 5 i2addr. 4 i2addr. 3 i2addr. 2 i2addr. 1 i2addr. 0 mnemonic: i2addr address: c1h bit name function 7~1 i2addr.7 ~ i2addr1 i2c address register: the 8051 uc can read from and write to this 8-bit, directly addressable sfr. the content of this register is irrelevant when i2c is in master mode. in the slave mode, the seven most significant bi ts must be loaded with the mcu?s own address. the i2c hardware will react if either of the address is matched. 0 gc general call function. 0: disable general call function. 1: enable general call function. non address bit: 7 6 5 4 3 2 1 0 nvmad dr.7 nmvad dr.6 nvmad dr.5 nvmad dr.4 nvmad dr.3 nvmad dr.2 nvmad dr.1 nvmad dr.0 mnemonic: nvmaddr address: c6h bit name function 7~0 nvmaddr.7 ~ nvmaddr.0 the nvm address: the register indicates nvm data memory of low byte address on on-chip code memory space.
w79e825/824/823a/822a/821a data sheet - 36 - timed access bit: 7 6 5 4 3 2 1 0 ta.7 ta.6 ta.5 ta.4 ta.3 ta.2 ta.1 ta.0 mnemonic: ta address: c7h bit name function 7~0 ta the timed access register: the timed access register cont rols the access to protected bits. to access protected bits, the user must first write aah to the ta. this must be immediately followed by a write of 55h to ta. now a window is opened in the protected bits for three machine cycles, during which the user can write to these bits. nvm control bit: 7 6 5 4 3 2 1 0 eer ewr - - - - - - mnemonic: nvmcon address: ceh bit name function 7 eer nvm page(n) erase bit. 0: without erase nvm page(n). 1: set this bit to erase nvm data of p age(n) to ffh. the nvm has 4 pages and each page have 64 bytes data memory. before sele ct page by nvmaddr register that will automatic enable page area, after set this bit, the page will be erased and program counter will halt at this instruction. afte r finished, program counter will kept next instruction then executed. the nvm p age?s address define as below table. 6 ewr nvm data write bit 0: without write nvm data. 1: set this bit to write nvm bytes and program counter will halt at this instruction. after write is finished, program counter w ill kept next instruct ion then executed. 5~0 - reserved nvm page(n) area definition table: page start address end address 0 00h 3fh 1 40h 7fh 2 80h bfh 3 c0h ffh note: the w79e823, w79e822 and w79e 821 without page 2 and page 3.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 37 - revision a2 nvm data bit: 7 6 5 4 3 2 1 0 nvmda t .7 nvmda t .6 nvmda t .5 nvmda t .4 nvmda t .3 nvmda t .2 nvmda t .1 nvmda t .0 mnemonic: nvmdata address: cfh bit name function 7~0 nvmdat.7 ~ nvmdat.0 the nvm data write register. the read nvm data is by movc instruction. program status word bit: 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p mnemonic: psw address: d0h bit name function 7 cy carry flag: set for an arithmetic operation which result s in a carry being generated from the alu. it is also used as the accumulator for the bit operations. 6 ac auxiliary carry: set when the previous operation resulted in a carry from the high order nibble. 5 f0 user flag 0: the general purpose flag that can be set or cleared by the user. 4 rs1 register bank select bits: 3 rs0 register bank select bits: 2 ov overflow flag: set when a carry was generated from the sev enth bit but not from the 8th bit as a result of the previous operation, or vice-versa. 1 f1 user flag 1: the general purpose flag that can be set or cleared by the user by software. 0 p parity flag: set/cleared by hardware to indicate odd/ev en number of 1's in the accumulator.
w79e825/824/823a/822a/821a data sheet - 38 - rs.1-0: register bank selection bits: rs1 rs0 register bank address 0 0 0 00-07h 0 1 1 08-0fh 1 0 2 10-17h 1 1 3 18-1fh pwm counter high bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwmp.9 pwmp.8 mnemonic: pwmph address: d1h bit name function 7~2 - reserved 1~0 pwmp.9 ~pwmp.8 the pwm counter register bit9~8. pwm 0 high bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwm0.9 pwm0.8 mnemonic: pwm0h address: d2h bit name function 7~2 - reserved 1~0 pwm0.9 ~pwm0.8 the pwm 0 high bits register bit 9~8. pwm 1 high bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwm1.9 pwm1.8 mnemonic: pwm1h address: d3h
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 39 - revision a2 bit name function 7~2 - reserved 1~0 pwm1.9 ~pwm1.8 the pwm1 high bits register bit 9~8. pwm 2 high bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwm2.9 pwm2.8 mnemonic: pwm2h address: d5h bit name function 7~2 - reserved 1~0 pwm2.9 ~pwm2.8 the pwm2 high bits register bit 9~8. note: the w79e823, w79e822 and w 79e821 without pwm2h register. pwm 3 high bits register bit: 7 6 5 4 3 2 1 0 - - - - - - pwm3.9 pwm3.8 mnemonic: pwm3h address: d6h bit name function 7~2 - reserved 1~0 pwm3.9 ~pwm3.8 the pwm3 high bits register bit 9~8. note: the w79e823, w79e822 and w 79e821 without pwm3h register. pwm control register 3 bit: 7 6 5 4 3 2 1 0 - - - - - - - bkf mnemonic: pwmcon3 address: d7h
w79e825/824/823a/822a/821a data sheet - 40 - bit name function 7~1 - reserved 0 bkf the external brake pin flag. 0: the pwm is not brake. 1: the pwm is brake by external br ake pin. it will be cleared by software. watchdog control bit: 7 6 5 4 3 2 1 0 wdrun - wd1 wd0 wdif wtrf ewrst wdclr mnemonic: wdcon address: d8h bit name function 7 wdrun 0: the watchdog is stopped 1: the watchdog is running. 6 - reserved. 5 wdi watchdog timer times selected. 4 wd0 watchdog timer times selected. 3 wdif watchdog timer interrupt flag 0: if the interrupt is not enabled, then this bit indicates that the time-out period has elapsed. this bit must be cleared by software. 1: if the watchdog interrupt is enabled, hardware will set this bit to indicate that the watchdog interrupt has occurred. 2 wtrf watchdog timer reset flag 1: hardware will set this bit when the watchdog timer causes a reset. software can read it but must clear it manually. a power-f ail reset will also clear the bit. this bit helps software in determining the cause of a reset. if ewrst = 0, the watchdog timer will have no affect on this bit. 1 ewrst 0: disable watchdog timer reset. 1: enable watchdog timer reset. 0 wdclr reset watchdog timer this bit helps in putting the watchdog timer into a know state. it also helps in resetting the watchdog timer before a time-out occurs. failing to set the ewrstt before time- out will cause an interrupt, if ewdi (ie1.4) is set, and 512 clocks after that a watchdog timer reset will be generated if ewrst is set. this bit is self-clearing by hardware.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 41 - revision a2 the wdcon sfr is set to a 0x0000x0b on an reset. wtrf (wdcon.2) is set to a 1 on a watchdog timer reset, but to a 0 on power on/down resets. wdif (wdcon.3) is not altered by an external reset. por is set to 1 by a power-on reset. ewrst (wdcon.1) is set to 0 on a power-on reset and unaffected by other resets. all the bits in this sfr have unrestricted r ead access. por, ewrst, wdif and wdclr require timed access procedure to write. the remaining bi ts have unrestricted write accesses. please refer ta register description. ta reg c7h wdcon reg d8h ckcon reg 8eh mov ta, #aah mov ta, #55h setb wdcon.0 ; reset watchdog timer orl ckcon, #11000000b ; select 26 bits watchdog timer mov ta, #aah mov ta, #55h orl wdcon, #00000010b ; enable watchdog pwm counter low bits register bit: 7 6 5 4 3 2 1 0 pwmp.7 pwmp.6 pwmp.5 pwmp .4 pwmp.3 pwmp.2 pwmp.1 pwmp.0 mnemonic: pwmpl address: d9h bit name function 7~0 pwmp.7 ~pwmp.0 pwm counter low bits register. pwm 0 low bits register bit: 7 6 5 4 3 2 1 0 pwm0.7 pwm0.6 pwm0.5 pwm0 .4 pwm0.3 pwm0.2 pwm0.1 pwm0.0 mnemonic: pwm0l address: dah
w79e825/824/823a/822a/821a data sheet - 42 - bit name function 7~0 pwm0.7 ~pwm0.0 pwm 0 low bits register. pwm 1 low bits register bit: 7 6 5 4 3 2 1 0 pwm1.7 pwm1.6 pwm1.5 pwm1 .4 pwm1.3 pwm1.2 pwm1.1 pwm1.0 mnemonic: pwm1l address: dbh bit name function 7~0 pwm1.7 ~pwm1.0 pwm 1 low bits register. pwm control register 1 bit: 7 6 5 4 3 2 1 0 pwmrun load cf clrpwm pwm3i pwm2i pwm1i pwm0i mnemonic: pwmcon1 address: dch bit name function 7 pwmrun 0: the pwm is not running. 1: the pwm counter is running. 6 load 0: the registers value of pwmp and co mparators are never loaded to counter and comparator registers. 1: the pwmp register will be load value to counter register after counter underflow, and hardware will clear by next clock cycle. 5 cf 0: the 10-bit counter down count is not underflow. 1: the 10-bit counter down count is underflow. it will be cleared by software. 4 clrpwm 1: clear 10-bit pwm counter to 000h. 3 pwm3i 0: pwm3 out is non-inverted. 1: pwm3 output is inverted. 2 pwm2i 0: pwm2 out is non-inverted. 1: pwm2 output is inverted. 1 pwm1i 0: pwm1 out is non-inverted. 1: pwm1 output is inverted. 0 pwm0i 0: pwm0 out is non-inverted. 1: pwm0 output is inverted. note: the w79e823, w79e822 and w79e821 wi thout pwm2i and pwm3i bit control.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 43 - revision a2 pwm 2 low bits register bit: 7 6 5 4 3 2 1 0 pwm2.7 pwm2.6 pwm2.5 pwm2 .4 pwm2.3 pwm2.2 pwm2.1 pwm2.0 mnemonic: pwm2l address: ddh bit name function 7~0 pwm2.7 ~pwm2.0 pwm 2 low bits register. note: the w79e823, w79e822 and w 79e821 without pwm2l register. pwm 3 low bits register bit: 7 6 5 4 3 2 1 0 pwm3.7 pwm3.6 pwm3.5 pwm3 .4 pwm3.3 pwm3.2 pwm3.1 pwm3.0 mnemonic: pwm3l address: deh bit name function 7~0 pwm3.7 ~pwm3.0 pwm 3 low bits register. note: the w79e823, w79e822 and w 79e821 without pwm3l register. pwm control register 2 bit: 7 6 5 4 3 2 1 0 bkch bkps bpen bken pwm3b pwm2b pwm1b pwm0b mnemonic: pwmcon2 address: dfh bit name function 7 bkch see the below table, when bken is set. 6 bkps 0: brake is asserted if p0.2 is low. 1: brake is asserted if p0.2 is high 5 bpen see the below table, when bken is set. 4 bken 0: the brake is never asserted. 1: the brake is enabled, and see the below table. 3 pwm3b 0: the pwm3 output is low, when brake is asserted. 1: the pwm3 output is high, when brake is asserted.
w79e825/824/823a/822a/821a data sheet - 44 - contiuned bit name function 2 pwm2b 0: the pwm2 output is low, when brake is asserted. 1: the pwm2 output is high, when brake is asserted. 1 pwm1b 0: the pwm1 output is low, when brake is asserted. 1: the pwm1 output is high, when brake is asserted. 0 pwm0b 0: the pwm0 output is low, when brake is asserted. 1: the pwm0 output is high, when brake is asserted. note: the w79e823, w79e822 and w79e821 wi thout pwm2b and pwm3b bit control. brake condition table bpen bkch brake condition 0 0 brake on, software brake by bken. 0 1 on, when pwm is not running(pwmrun= 0), the pwm output condition is follow pwmnb setting. off, when pwm is running(pwmrun=1). 1 0 brake on, when brake pin asserted, no pwm output, the bit of pwmrun will be cleared and bkf flag will be set. 1 1 no any active. accumulator bit: 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 acc. 4 acc.3 acc.2 acc.1 acc.0 mnemonic: acc address: e0h acc.7-0: the a (or acc) register is the standard 8052 accumulator. adc control register bit: 7 6 5 4 3 2 1 0 adc.1 adc.0 adcex a dci adcs rcclk aadr1 aadr0 mnemonic: adccon address: e1h bit name function 7 adc.1 the adc conversion result. 6 adc.0 the adc conversion result. 5 adcex enable stadc-triggered conversion 0: conversion can only be started by software (i.e., by setting adcs). 1: conversion can be started by software or by a rising edge on stadc (pin p1.4). 4 adci adc interrupt flag: this flag is set w hen the result of an a/d conversion is ready. this generates an adc interrupt, if it is enabled. the flag may be cleared by the isr. while this flag is 1, the adc cannot start a new conversion. adci can not be set by software.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 45 - revision a2 continued bit name function 3 adcs adc start and status: set this bit to start an a/d conversion. it may also be set by stadc if adcex is 1. this signal remain s high while the adc is busy and is reset right after adci is set. adcs can not be re set by software, and the adc cannot start a new conversion while adcs is high. adci adcs adc status 0 0 1 1 0 1 0 1 adc not busy; a conversion can be started adc busy; start of a new conversion is blocked conversion completed; start of a new conversion requires adci=0 conversion completed; start of a new conversion requires adci=0 it is recommended to clear adci before adcs is set. however, if adci is cleared and adcs is set at the same time, a new a/d conversion may start on the same channel. 2 rcclk 0: the cpu clock is used as adc clock. 1: the internal rc clock is used as adc clock. 1 aadr1 the adc input select. see table below. 0 aadr0 the adc input select. see table below. aadr1, aadr0: adc analog input channel select bits: these bits can only be changed when adci and adcs are both zero. aadr1 aadr0 selected analog input channel 0 0 ad0 (p0.3) 0 1 ad1 (p0.4) 1 0 ad2 (p0.5) 1 1 ad3 (p0.6) adc converter result register bit: 7 6 5 4 3 2 1 0 adc.9 adc.8 adc.7 adc. 6 adc.5 adc.4 adc.3 adc.2 mnemonic: adch address: e2h bit name function 7~0 adc.9 ~adc.2 the adc conversion result.
w79e825/824/823a/822a/821a data sheet - 46 - interrupt enable register 1 bit: 7 6 5 4 3 2 1 0 - - epwm ewdi ec2 ec1 ekb ei2 mnemonic: ie1 address: e8h bit name function 7 - reserved. 6 - reserved. 5 epwm 0: disable pwm interrupt w hen external brake pin was brake. 1: enable pwm interrupt when external brake pin was brake. 4 ewdi 0: disable watchdog timer interrupt. 1: enable watchdog timer interrupt. 3 ec2 0: disable comparator 2 interrupt. 1: enable comparator 2 interrupt. 2 ec1 0: disable comparator 1 interrupt. 1: enable comparator 1 interrupt. 1 ekb 0: disable keypad interrupt. 1: enable keypad interrupt. 0 ei2 0: disable i2c interrupt. 1: enable i2c interrupt. b register bit: 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 mnemonic: b address: f0h b.7-0: the b register is the standard 8052 regist er that serves as a second accumulator. port 0 digital input disable bit: 7 6 5 4 3 2 1 0 p0id.7 p0id.6 p0 id.5 p0id.4 p0id.3 p0id .2 p0id.1 p0id.0 mnemonic: p0id address: f6h
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 47 - revision a2 bit name function 7~0 p0id.7 ~p0id.0 enable/disable port 0 digital inputs. 0: enable port 0 digital inputs. 1: disable port 0 digital inputs. interrupt high priority 1 bit: 7 6 5 4 3 2 1 0 - - ppwmh pwdih pc2h pc1h pkbh pi2h mnemonic: ip1h address: f7h bit name function 7 - reserved. 6 - reserved. 5 ppwmh 1: to set interrupt high priority of pwm?s brake is highest priority level. 4 pwdih 1: to set interrupt high priority of watchdog is highest priority level. 3 pc2h 1: to set interrupt high priority of co mparator 2 is highest priority level. 2 pc1h 1: to set interrupt high priority of co mparator 1 is highest priority level. 1 pkbh 1: to set interrupt high priority of keypad is highest priority level. 0 pi2h 1: to set interrupt high priority of i2c is highest priority level. interrupt priority 1 bit: 7 6 5 4 3 2 1 0 - - ppwm pwdi pc2 pc1 pkb pi2 mnemonic: ip1 address: f8h bit name function 7 - reserved. 6 - reserved. 5 ppwm 1: to set interrupt priority of pwm?s ex ternal brake is higher priority level. 4 pwdi 1: to set interrupt priority of watchdog is higher priority level. 3 pc2 1: to set interrupt priority of com parator 2 is higher priority level. 2 pc1 1: to set interrupt priority of com parator 1 is higher priority level. 1 pkb 1: to set interrupt priority of keypad is higher priority level. 0 pi2 1: to set interrupt priority of i2c is higher priority level.
w79e825/824/823a/822a/821a data sheet - 48 - 10. instruction the w79e82x series execute all the instructions of the standard 8052 family. the operation of these instructions, their effect on the fl ag bits and the status bits is exac tly the same. however, timing of these instructions is different. the reason for this is two fold. firstly, in the w79e82x series, each machine cycle consists of 4 clock periods, while in the standard 8052 it consists of 12 clock periods. also, in the w79e82x series there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard 8052 there can be two fetches per machine cycle, which works out to 6 clocks per fetch. the advantage the w79e82x series has is that since there is only one fetch per machine cycle, the number of machine cycles in most cases is equal to the number of operands t hat the instruction has. in case of jumps and calls there will be an additi onal cycle that will be needed to calculate the new address. but overall the w79e82x serial reduces the number of dummy fetches and wasted cycles, thereby improving efficiency as compared to the standard 8052. table: instructions affect flag setting instruction carry overflow auxiliary carry instruction carry overflow auxiliary carry add x x x clr c 0 addc x x x cpl c x subb x x x anl c, bit x mul 0 x anl c, bit x div 0 x orl c, bit x da a x orl c, bit x rrc a x mov c, bit x rlc a x cjne x setb c 1 a "x" indicates that the modification is as per the result of instruction. 10.1 instruction timing the instruction timing for the w79e82x series are an important aspect, especially for those users who wish to use software instructions to generate timing del ays. also, it provides the user with an insight into the timing differences between the w79e82x series and the standard 8052. in the w79e82x series each machine cycle is four clock periods l ong. each clock period is designated a state. thus each machine cycle is made up of four states, c1, c2 c3 and c4, in that order. due to the reduced time for each instruction executi on, both the clock edges are used for internal timing. hence it is important that the duty cycle of t he clock be as close to 50% as possible to avoid timing conflicts. as mentioned earlier, the w79e82x series does one op-code fetch per machine cycle. therefore, in most of the instru ctions, the number of machine cycl es needed to execute the instruction is equal to the number of bytes in the instructi on. of the 256 available op-codes, 128 of them are single cycle instructions. thus more than half of a ll op-codes in the w79e82x series are executed in just four clock periods. most of the two-cycle instructions are thos e that have two byte instruction codes. however there are some instructions that have only one byte instructions, yet they are two cycle instructions. one instructi on which is of importance is the movx instruction. in the standard 8052, the movx instruction is always two machine cycles long. however, in the w79e82x series each machine cycle is made of only 4 clock periods compared to the 12 clock periods for the standard 8052. therefore, even though the number of categories has increased, eac h instruction is at least 1.5 to 3 times faster than the standard 8052 in terms of clock periods.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 49 - revision a2 single cycle c4 c3 c2 c1 cpu clk ale psen ad<7:0> address <15:0> a7-0 address a15-8 data_ in d7-0 single cycle instruction timing instruction fetch c4 c3 c2 c1 op-code address a15-8 address a15-8 ale psen pc ad<7:0> a ddress<15:0> cpu clk operand fetch c4 c3 c2 c1 operand pc+1 two cycle instruction timing
w79e825/824/823a/822a/821a data sheet - 50 - operand operand a7-0 a7-0 a7-0 op-code address a15-8 address a15-8 address a15-8 operand fetch operand fetch instruction fetch c2 c3 c4 c2 c3 c4 c4 c3 c2 c1 c1 c1 cpu clk ale psen ad<7:0> a ddress<15:0> three cycle instruction timing operand operand operand op-code address a15-8 address a15-8 address a15-8 address a15-8 a7-0 a7-0 a7-0 a7-0 operand fetch operand fetch operand fetch instruction fetch c2 c1 c4 c3 c2 c1 cpu clk ale psen ad<7:0> a ddress<15:0> c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 four cycle instruction timing
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 51 - revision a2 operand operand operand op-code address a15-8 address a15-8 address a15-8 address a15-8 a7-0 a7-0 a7-0 a7-0 operand fetch operand fetch operand fetch operand fetch instruction fetch c2 c1 c4 c3 c2 c1 cpu clk ale psen ad<7:0> a ddress<15:0> c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 operand a7-0 address a15-8 five cycle instruction timing
w79e825/824/823a/822a/821a data sheet - 52 - 11. power management the w79e82x series provide idle mode and power- down mode to control power consumption. these modes are discussed in the next two secti ons, followed by a discussion of resets. 11.1 idle mode the user can put the device into idle mode by writing 1 to the bit pcon.0. the instruction that sets the idle bit is the last instruction that will be execut ed before the device goes into idle mode. in the idle mode, the clock to the cpu is hal ted, but not to the interrupt, timer, watchdog timer and serial port blocks. this forces the cpu state to be frozen; t he program counter, the stack pointer, the program status word, the accumulator and the other regist ers hold their contents. the port pins hold the logical states they had at the time idle was acti vated. the idle mode can be terminated in two ways. since the interrupt controller is still active, the activation of any enabled interrupt can wake up the processor. this will automatically clear the idle bi t, terminate the idle mode, and the interrupt service routine (isr) will be executed. a fter the isr, execution of the program will continue from the instruction which put the device into idle mode. the idle mode can also be exited by activating the reset. the device can put into reset either by applying a low on the external rst pin, a power on reset condition or a watchdog timer reset. the external reset pin has to be held high for at leas t two machine cycles i.e. 8 clock periods to be recognized as a valid reset. in the reset conditi on the program counter is reset to 0000h and all the sfrs are set to the reset condition. since the clo ck is already running there is no delay and execution starts immediately. in the idle mode, the watchdog timer continues to run, and if enabled, a time-out will cause a watchdog timer interrupt which will wa ke up the device. the software must reset the watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out. when the w79e82x series are exiting from an idle mode with a reset, the instruction following the one which put the device into idle mode is not exec uted. so there is no danger of unexpected writes. 11.2 power down mode the device can be put into power down mode by writ ing 1 to bit pcon.1. the instruction that does this will be the last instruction to be executed bef ore the device goes into power down mode. in the power down mode, all the clocks are stopped and the devic e comes to a halt. all activity is completely stopped and the power consumption is reduced to the lo west possible value. the port pins output the values held by their respective sfrs. the w79e82x serial will exit the power down mode with a reset or by an external interrupt pin enabled as level detected. an external reset can be used to exit the power down state. the low on rst pin terminates the power down mode, and restar ts the clock. the program execution will restart from 0000h. in the power down mode, the clock is stopped, so the watchdog timer cannot be used to provide the reset to exit power down mode. the w79e82x series can be woken from the power down mode by forcing an external interrupt pin activated, provided the corresponding interrupt is enabled, while the global enable(ea) bit is set and the external input has been set to a level detect m ode. if these conditions are met, then the high level on the external pin re-starts the oscillator. then dev ice executes the interrupt service routine for the corresponding external interrupt. after the interrupt service routine is completed, the program execution returns to the instruction after one which put the device into power down mode and continues from there. during power down mode, if auxr1.lpbov = 1 and auxr1.bod = 0, the internal rc clock will be enabled and hence save power.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 53 - revision a2 12. reset conditions the user has several hardware related options for pl acing the w79e82x series into reset condition. in general, most register bits go to their reset value irre spective of the reset condition, but there are a few flags whose state depends on the source of reset. the user can use these flags to determine the cause of reset using software. 12.1 external reset the device continuously samples the rst pin at state c4 of every ma chine cycle. therefore the rst pin must be held for at least 2 machine cycles to ensure detection of a valid rst low. the reset circuitry then synchronously applies the internal reset signal. thus the reset is a synchronous operation and requires the clock to be running to cause an external reset. once the device is in reset condition, it will rema in so as long as rst is 0. even after rst is deactivated, the device will continue to be in rese t state for up to two machine cycles, and then begin program execution from 0000h. there is no flag associ ated with the external reset condition. however since the other two reset sources have flags, the ex ternal reset can be considered as the default reset if those two flags are cleared. 12.2 power-on reset (por) the software must clear the por flag after reading i t. otherwise it will not be possible to correctly determine future reset sources. if the power fails, i.e. falls below vrst, then the device will once again go into reset state. when the power returns to the proper operating levels, the device will again perform a power on reset delay and set the por flag. 12.3 watchdog timer reset the watchdog timer is a free running timer with progra mmable time-out intervals. the user can clear the watchdog timer at any time, causing it to restar t the count. when the time-out interval is reached an interrupt flag is set. if the watchdog reset is enabled and the watchdog timer is not cleared, then 512 clocks from the flag being set, the watchdog time r will generate a reset. this places the device into the reset condition. the reset condition is ma intained by hardware for two machine cycles. once the reset is removed the devic e will begin execution from 0000h. 12.4 reset state most of the sfrs and registers on the device will go to the same condition in the reset state. the program counter is forced to 0000h and is held ther e as long as the reset condition is applied. however, the reset state does not affect the on- chip ram. the data in the ram will be preserved during the reset. however, the stack pointer is re set to 07h, and therefore the stack contents will be lost. the ram contents will be lost if the v dd falls below approximately 2v, as this is the minimum voltage level required for the ram to operate normally. therefore after a first time power on reset the ram contents will be indeterminate. during a power fa il condition, if the power falls below 2v, the ram contents are lost. after a reset most sfrs are cleared. interrupt s and timers are disabled. the watchdog timer is disabled if the reset source was a por. the sfrs have ffh written into them which puts the port pins in a high state.
w79e825/824/823a/822a/821a data sheet - 54 - sfr reset value sfr name reset value sfr name reset value p0 11111111b i2dat xxxxxxxxb sp 00000111b i2status 00000xxxb dpl 00000000b i2timer 00000000b dph 00000000b i2clk 00000000b pcon 00xx0000b i2con 00000000b tcon 00000000b i2addr xxxxxxxxb tmod 00000000b ta 00000000b tl0 00000000b psw 00000000b tl1 00000000b pwmp1 xxxxxx00b th0 00000000b pwm0h xxxxxx00b th1 00000000b pwm1h xxxxxx00b ckcon 00000000b pwm2h xxxxxx00b p1 1111xx11b pwm3h xxxxxx00b divm 00000000b wdcon 0x000000b scon 00000000b pwmp0 00000000b sbuf xxxxxxxxb pwm0l 00000000b p2 xxxxx11b pwm1l 00000000b kbi 00000000b pwmcon1 00000000b auxr1 00000000b pwm2l 00000000b ie 00000000b pwm3l 00000000b saddr 00000000b pwmcon2 00000000b cmp1 00000000b acc 00000000b cmp2 00000000b adccon xx000x00b p0m1 00000000b adch xxxxxxxxb p0m2 00000000b ie1 xx000000b p1m1 00000000b b 00000000b p1m2 00000000b p0ids 00000000b p2m1 00000000b iph xx000000b p2m2 xxxxxx00b ip1 xx000000b ip0h x0000000b ip0 x0000000b saden 00000000b
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 55 - revision a2 the wdcon sfr bits are set/cleared in rese t condition depending on the source of the reset. external reset watchdog reset power on reset wdcon 0x0x0xx0b 0x0x01x0b 01000000b the por bit wdcon.6 is set only by the power on reset. the pfi bit wdcon.4 is set when the power fail condition occurs. however, a power-on rese t will clear this bit. the wtrf bit wdcon.2 is set when the watchdog timer causes a reset. a power on reset will also clear this bit. the ewrst bit wdcon.1 is cleared by power on resets. this di sables the watchdog timer resets. a watchdog or external reset does not affect the ewrst bit.
w79e825/824/823a/822a/821a data sheet - 56 - 13. interrupts the w79e82x series have four priority level interrupt s structure with 13 interrupt sources. each of the interrupt sources has an individual priority bit, fl ag, interrupt vector and enable bit. in addition, the interrupts can be globally enabled or disabled. 13.1 interrupt sources the external interrupts int0 and int1 can be either edge triggered or level triggered, depending on bits it0 and it1. the bits ie0 and ie1 in the tcon register are the flags which are checked to generate the interrupt. in the edge triggered mode, t he intx inputs are sampled in every machine cycle. if the sample is high in one cycle and low in the next, then a high to low transition is detected and the interrupts request flag iex in tcon is se t. the flag bit requests the interrupt. since the external interrupts are sampled every machine cycle, they have to be held high or low for at least one complete machine cycle. the iex flag is automatica lly cleared when the service routine is called. if the level triggered mode is selected, then the requesting sour ce has to hold the pin low till the interrupt is serviced. the iex flag will not be cleared by the hardware on entering the service routine. if the interrupt continues to be held low even after the serv ice routine is completed, then the processor may acknowledge another interrupt r equest from the same source. the timer 0 and 1 interrupts are generated by the tf0 and tf1 flags. these flags are set by the overflow in the timer 0 and timer 1. the tf0 and tf1 flags are automatically cleared by the hardware when the timer interrupt is serviced. t he watchdog timer can be used as a system monitor or a simple timer. in either case, when the time -out count is reached, the watchdog timer interrupt flag wdif (wdcon.3) is set. if the interrupt is enabled by the enable bit ie1.4, then an interrupt will occur. the serial block can generate interrupt on reception or transmission. there are two interrupt sources from the serial block, which are obtained by the ri and ti bits in t he scon sfr. these bits are not automatically cleared by the hardw are, and the user will have to cl ear these bits using software. all the bits that generate interrupts can be set or reset by hardware, and thereby software initiated interrupts can be generated. each of the individual interrupts can be enabled or disabled by setting or clearing a bit in the ie sfr. ie also has a global enable/disable bit ea, which can be cleared to disable all interrupts. the adc can generate interrupt after finished adc conv erter. there is one interrupt source, which is obtained by the adci bit in the a dccon sfr. this bit is not automat ically cleared by the hardware, and the user will have to clear this bit using software. the two comparators can generate interrupt after co mparator output has toggle occurs by cmf1 and cmf2. these bits are not automatically cleared by the hardware, and the user will have to clear these bits using software. the i2c function can generate interrupt by si flag, a fter i2c finished some action, then si will set by hardware. if interrupt of i2c is enabled, it will gener ate interrupt. this bit will clear by software. the pwm function can generate interrupt by bkf flag, after external brake pin has brake occurred. this bit will clear by software.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 57 - revision a2 13.2 priority level structure there are four priority levels for the interrupts, highest, high, low and lowest. the interrupt sources can be individually set to either high or low leve ls. naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. howeve r there exists a pre-defined hierarchy amongst the interrupts themselves. this hierarchy comes into play when the interrupt controller has to resolve simultaneous requests having the same priority level. this hierarchy is defined as shown below; the interrupts are numbered starting from t he highest priority to the lowest. priority structure of interrupts source flag priority level external interrupt 0 ie0 1(highest) brownout detect bof 2 watchdog timer wdif 3 timer 0 overflow tf0 4 i2c interrupt si 5 adc interrupt adci 6 external interrupt 1 ie1 7 kbi interrupt kbf 8 comparator 1 interrupt cmf1 9 timer 1 overflow tf1 10 comparator 2 interrupt cmf2 11 serial port ri + ti 12 pwm bkf 13 (lowest) the interrupt flags are sampled every machine cy cle. in the same machine cycle, the sampled interrupts are polled and their priority is resolved. if certain conditions are met then the hardware will execute an internally generated lca ll instruction which will vector the process to the appropriate interrupt vector address. the condi tions for generating the lcall are 1. an interrupt of equal or higher prio rity is not currently being serviced. 2. the current polling cycle is the last machine cycle of the instruction currently being execute. 3. the current instruction does not involve a write to ie, ie1, ip0, ip0h, ip1 or iph1 registers and is not a reti. if any of these conditions are not met, then the lcall will not be generated. the polling cycle is repeated every machine cycle, with the interrupts sampled in the same machine cycle. if an interrupt flag is active in one cycle but not responded to, and is not active when the above conditions are met, the denied interrupt will not be serviced. this means that active interrupts are not remembered; every polling cycle is new.
w79e825/824/823a/822a/821a data sheet - 58 - the processor responds to a valid interrupt by executing an lcall instruction to the appropriate service routine. this may or may not clear the flag which caused the interrupt. in case of timer interrupts, the tf0 or tf1 flags are cleared by hardware whenever the processor vectors to the appropriate timer service routine. in case of exte rnal interrupt, int0 and int1, the flags are cleared only if they are edge triggered. in case of serial in terrupts, the flags are not cleared by hardware. in the case of timer 2 interrupt, the flags are not cleared by hardware. the watchdog timer interrupt flag wdif has to be cleared by software. the hardwar e lcall behaves exactly like the software lcall instruction. this instruction saves the program c ounter contents onto the sta ck, but does not save the program status word psw. the pc is reloaded with the vector address of that interrupt which caused the lcall. these address of vector for the different sources are as follows vector locations for interrupt sources source vector address source vector address external interrupt 0 0003h timer 0 overflow 000bh external interrupt 1 0013h timer 1 overflow 001bh serial port 0023h brownout interrupt 002bh i2c interrupt 0033h kbi interrupt 003bh comparator 2 interrupt 0043h - 004bh watchdog timer 0053h adc interrupt 005bh comparator 1 interrupt 0063h - 006bh pwm brake interrupt 0073h - 007bh four-level interrupt priority priority bits ipxh ipx interrupt priority level 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) the vector table is not evenly spac ed; this is to accommodate future expansions to the device family. execution continues from the vect ored address till an reti instruction is executed. on execution of the reti instruction the processor pops the stack and loads the pc with the contents at the top of the stack. the user must take care that the status of t he stack is restored to what is was after the hardware lcall, if the execution is to return to the interrupted program. the processor does not notice anything if the stack cont ents are modified and will proceed with execution from the address put back into pc. note that a ret instruction woul d perform exactly the same process as a reti instruction, but it would not inform the interrupt controller that the inte rrupt service routine is completed, and would leave the controller still th inking that the service routine is underway.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 59 - revision a2 the w79e82x series use a four priority level inte rrupt structure. this allows great flexibility in controlling the handling of the w79e82x series m any interrupt sources. the w79e82x series supports up to 13 interrupt sources. each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers ien0 or ien1. the ien0 register also contains a gl obal disable bit, ea, which disables all interrupts at once. each interrupt source can be individually programm ed to one of four priority levels by setting or clearing bits in the ip0, ip0h, ip1, and ip1h regist ers. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interr upted by any other interrupt source. so, if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. this is called the arbitration rank ing. note that the arbitration ranking is only used to resolve simultaneous requests of the same priority level. as below table summarizes the interrupt sources, fl ag bits, vector addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may wake up the cpu from power down mode. description interrupt flag bit(s) vector address interrupt enable bit(s) interrupt priority arbitration ranking power down wakeup external interrupt 0 ie0 0003h ex0 (ie0.0) ip0h.0, ip0.0 1(highest) yes brownout detect bof 002bh ebo (ie.5) ip0h.5, ip0.5 2 yes watchdog timer wdif 0053h ewdi (ie1.4) ip1h.4, ip1.4 3 yes timer 0 interrupt tf0 000bh et0 (ie.1) ip0h.1, ip0.1 4 no i2c interrupt si 0033h ei2 (ie1.0) ip1h.0, ip1.0 5 no adc converter adci 005bh ead (ie.6) ip0h.6, ip0.6 6 yes external interrupt 1 ie1 0013h ex1 (ie.2) ip0h.2, ip0.2 7 yes kbi interrupt kbf 003bh ekb (ie1.1) ip1h.1, ip1.1 8 yes comparator 1 interrupt cmf1 0063h ec1 (ie1.2) ip1h.2, ip1.2 9 yes timer 1 interrupt tf1 001bh et1 (ie.3) ip0h.3, ip0.3 10 no comparator 2 interrupt cmf2 0043h ec2 (ie1.3) ip1h.3, ip1.3 11 yes serial port tx and rx ti & ri 0023h es (ie.4) ip0h.4, ip0.4 12 no pwm interrupt bkf 0073h epwm (ie1.5) ip1h.5, ip1.5 13 (lowest) no
w79e825/824/823a/822a/821a data sheet - 60 - 13.3 interrupt response time the response time for each interrupt source depends on several factors, such as the nature of the interrupt and the instruction underway. in the case of external interrupts int0 to ri+ti, they are sampled at c3 of every machine cycle and then t heir corresponding interrupt flags iex will be set or reset. the timer 0 and 1 overflow flags are set at c3 of the machine cycle in which overflow has occurred. these flag values are polled only in the next machine cycle. if a request is active and all three conditions are met, then the hardware generated lcall is executed. this lcall itself takes four machine cycles to be completed. thus there is a minimum time of five machine cycles between the interrupt flag being set and the inte rrupt service routine being executed. a longer response time should be anticipated if any of the three conditions are not met. if a higher or equal priority is being serviced, t hen the interrupt latency time obv iously depends on the nature of the service routine currently being exec uted. if the polling cycle is not the last machine cycle of the instruction being executed, then an additional delay is introduced. the maximum response time (if no other interrupt is in service) occu rs if the w79e82x series are perform ing a write to ie, ie1, ip0, ip0h, ip1 or ip1h and then executes a mul or div instru ction. from the time an interrupt source is activated, the longest reaction time is 12 machine cy cles. this includes 1 machine cycle to detect the interrupt, 2 machine cycles to complete the ie, ie1, ip0, ip0h, ip1 or ip1h access, 5 machine cycles to complete the mul or div instruction and 4 machi ne cycles to complete the hardware lcall to the interrupt vector location. thus in a single-interrupt system the interrupt response time will always be more than 5 machine cycles and not more than 12 machine cycles. the ma ximum latency of 12 machine cycles is 48 clock cycles. note that in the standard 8051 the maximu m latency is 8 machine cycles which equals 96 machine cycles. this is a 50% reduction in terms of clock periods. 13.4 interrupt inputs the w79e82x series have 13 interrupts source, and tw o individual interrupt inputs sources, one is for ie0,ie1, bof, kbf, wdt, adc, cmf1 and cmf2, and other is if0, if1, ri+ti ,si and bkf. two interrupt inputs are identical to those present on the standard 80c51 microcontroller as show in below figures. if an external interrupt is enabled when the w79e82x se ries are put into power down or idle mode, the interrupt will cause the processor to wake up and resume operation.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 61 - revision a2 ie0 ex0 ie1 ex1 bof ebo kbf ekb adci eadc wdt ewdi cm1 ec1 cm2 ec2 ea wakeup (if in power down) interrupt to cpu as below figure, those interrupt can?t be wakeup after power down. ei2 si es ri+ti et1 tf1 et0 tf0 ea interrupt to cpu bkf epwm
w79e825/824/823a/822a/821a data sheet - 62 - 14. programmable timers/counters the w79e82x series have two 16-bit progr ammable timer/counters and one programmable watchdog timer. the watchdog timer is operationally quite different from the other two timers. 14.1 timer/counters 0 & 1 the w79e82x series have two 16-bit timer/counters. each of these timer/counters has two 8 bit registers which form the 16 bit counting register. fo r timer/counter 0 they are th0, the upper 8 bits register, and tl0, the lower 8 bit register. similarl y timer/counter 1 has two 8 bit registers, th1 and tl1. the two can be configured to operate either as timers, counting machine cycles or as counters counting external inputs. when configured as a "timer", the timer counts cl ock cycles. the timer clock can be programmed to be thought of as 1/12 of t he system clock or 1/4 of the system clock. in the "counter" mode, the register is incremented on the falling edge of the external input pin, t0 in case of timer 0, and t1 for timer 1. the t0 and t1 inputs are sampled in every machine cycle at c4. if the sampled value is high in one machine cycle and low in the next, then a valid high to low transition on the pin is recognized and the count register is incremented. since it takes two machine cycles to recognize a negative transition on the pin, the maximum rate at which c ounting will take place is 1/24 of the master clock frequency. in either the "timer" or "counter" mode, the count register will be updated at c3. therefore, in the "timer" mode, the recognized negative transition on pin t0 and t1 can cause the count register value to be updated only in the ma chine cycle following the one in which the negative edge was detected. the "timer" or "counter" function is selected by the " t c/ " bit in the tmod special function register. each timer/counter has one selection bit for its own; bit 2 of tmod selects the function for timer/counter 0 and bit 6 of tmod selects the function for timer/counter 1. in addition each timer/counter can be set to operate in any one of four possible modes. the mode selection is done by bits m0 and m1 in the tmod sfr. 14.2 time-base selection the w79e82x series give the user two modes of operation for the timer. the timers can be programmed to operate like the standard 8051 family, count ing at the rate of 1/ 12 of the clock speed. this will ensure that timing loops on the w 79e82x series and the standard 8051 can be matched. this is the default mode of operati on of the w79e82x series timers. the user also has the option to count in the turbo mode, where the timers will incr ement at the rate of 1/4 clock speed. this will straight-away increase the counting speed three time s. this selection is done by the t0m and t1m bit in ckcon sfr. a reset sets these bits to 0, and the timers then operate in the standard 8051 mode. the user should set these bits to 1 if the timers are to operate in turbo mode. 14.3 mode 0 in mode 0, the timer/counters act as a 8-bit counter with a 5-bit, divide by 32 pre-scale. in this mode we have a 13-bit timer/counter. the 13-bit counter cons ists of 8 bits of thx and 5 lower bits of tlx. the upper 3 bits of tlx are ignored. the negative edge of the clock is incr ements count in the tlx register. when the fifth bit in tlx moves from 1 to 0, then the count in the thx register is incremented. when count in thx moves from ffh to 00h, then the overflow flag tfx in tcon sfr is set. the counted input is enabled only if trx is set
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 63 - revision a2 and either gate = 0 or intx = 1. when t c/ is set to 0, then it will count clock cycles, and if t c/ is set to 1, then it will count 1 to 0 transitions on t0 (p1.2) for timer 0 and t1 (p 0.7) for timer 1. when the 13-bit count reaches 1fffh the next count will cause it to roll-over to 0000h. the timer overflow flag tfx of the relevant timer is set and if enabled an interrupts will occur. fcpu 1/12 0 1 047 07 tfx th0 (th1) tl0 (tl1) timer 0/1 mode 0 interrupt t0oe t0=p1.2 (c/t=tmod.6) c/t=tmod.2 gate=tmod.3 (gate=tmod.7) int0=p1.3 (int1=p1.4) t1=(p0.7) p1.2 (p0.7) tf0 (tf1) tr0=tcon.4 tr1=tcon.6 (t1oe) 1/4 t0m=ckcon.3 (t1m=ckcon.4) 0 1 timer /counter mode 0 14.4 mode 1 mode 1 is similar to mode 0 except that the counting register form s a 16-bit counter, rather than a 13- bit counter. this means that all the bits of th x and tlx are used. roll-over occurs when the timer moves from a count of ffffh to 0000h. the timer overfl ow flag tfx of the relevant timer is set and if enabled an interrupt will occur. the selection of the ti me-base in the timer mode is similar to that in mode 0. the gate function operates similarly to that in mode 0. fcpu 1/12 0 1 047 07 tfx th0 (th1) tl0 (tl1) timer 0/1 mode 1 interrupt t0oe t0=p1.2 (c/t=tmod.6) c/t=tmod.2 gate=tmod.3 (gate=tmod.7) int0=p1.3 (int1=p1.4) t1=(p0.7) p1.2 (p0.7) tf0 (tf1) tr0=tcon.4 tr1=tcon.6 (t1oe) 1/4 0 1 t0m=ckcon.3 (t1m=ckcon.4) timer/counter mode 1
w79e825/824/823a/822a/821a data sheet - 64 - 14.5 mode 2 in mode 2, the timer/counter is in the auto rel oad mode. in this mode, tlx acts as a 8-bit count register, while thx holds the reload value. when the tlx register overflows from ffh to 00h, the tfx bit in tcon is set and tlx is reloaded with the c ontents of thx, and the c ounting process continues from here. the reload operation leaves the cont ents of the thx register unchanged. counting is enabled by the trx bit and proper setting of gate and intx pins. as in the other two modes 0 and 1 mode 2 allows counting of either clock cycles (clock/12 or clock/4) or pulses on pin tn. 0 1 07 07 tfx th0 (th1) tl0 (tl1) timer 0/1 mode 2 : 8-bit auto-reload mode interrupt t0oe t0=p1.2 (c/t=tmod.6) c/t=tmod.2 gate=tmod.3 (gate=tmod.7) int0=p1.3 (int1=p1.4) t1=(p0.7) p1.2 (p0.7) tf0 (tf1) tr0=tcon.4 tr1=tcon.6 (t1oe) fcpu 1/12 0 1/4 0 1 t0m=ckcon.3 (t1m=ckcon.4) timer/counter mode 2. 14.6 mode 3 mode 3 has different operating methods for the two ti mer/counters. for timer/c ounter 1, mode 3 simply freezes the counter. timer/counter 0, however, configures tl0 and th0 as two separate 8 bit count registers in this mode. the logic for this mode is shown in the figure. tl0 uses the timer/counter 0 control bits t c/ , gate, tr0, int0 and tf0. the tl0 can be used to count clock cycles (clock/12 or clock/4) or 1-to-0 transitions on pin t0 as determi ned by c/t (tmod.2). th0 is forced as a clock cycle counter (clock/12 or clock/4) and takes over the us e of tr1 and tf1 from timer/counter 1. mode 3 is used in cases where an extra 8 bit timer is needed. with timer 0 in mode 3, timer 1 can still be used in modes 0, 1 and 2., but its flexibility is somewhat lim ited. while its basic functionality is maintained, it no longer has control over its overflow flag tf1 and the enable bit tr1. timer 1 can still be used as a timer/counter and retains the use of gate and int1 pin. in this condition it can be turned on and off by switching it out of and into its own mode 3. it can also be used as a baud rate generator for the serial port.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 65 - revision a2 0 1 07 07 tf0 th0 tl0 timer 0/1 mode 3 : two 8-bit counters interrupt t0oe t0=p1.2 c/t=tmod.2 gate=tmod.3 int0=p1.3 p1.2 tr0=tcon.4 tr1=tcon.6 tf1 interrupt t1oe p0.7 fcpu 1/12 0 1/4 0 1 t0m=ckcon.3 (t1m=ckcon.4) timer/counter mode 3.
w79e825/824/823a/822a/821a data sheet - 66 - 15. nvm memory the w79e82x series hav e nvm data memory of 256/128 bytes for customer?s data store used. the nvm data memory has four/two pages area and each page has 64 bytes as below figure. the page 0 address is from fc00h ~ fc3fh , page 1 address is from fc40h ~ fc7fh , page 2 address is from fc80h ~ fcbfh , and page 3 address is from fcc0h ~ fcffh . the nvm memory can be read/write by customer program to access. read nvm data is by movc a,@a+dptr instruction, and writ e data is by sfr of nvmaddr, nvmdat and nvmcon. before write data to nvm memory, the page must be eras ed by set page address which low byte address of on-chip code memory space will decode and enable page(n) on nvmaddr, then set eer of nvmcon.7 will automatically hold fetch progr am code and pc counter, and execute page erase. after finished, this bit will be cleared by hardware. the erase time is ~ 5ms. by write data to nvm memory, user must set address and data to nvmaddr and nvmdat, therefore set ewr of nvmcon.6 to write data, then uc will hold program code and pc counter, then write data to mapping address, after finished, this bit will be cleared by hardware, the uc will continue execute next instruction. the program time is ~50us. 0000h external data memory space on-chip code memory space 0000h 16k/8k bytes on-chip code memory unused code memory unused code memory config 1 3fffh 4000h ffffh ffffh page 0 64 bytes page 1 64 bytes page 2 64 bytes page 3 64 bytes fc00h fc3fh fc40h fc7fh fc80h fcbfh fcc0h fcffh nvm data memory area fc00h config 2 fcffh 256 bytes nvm data memory unused data memory fbffh w79e825/w79e824 memory map
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 67 - revision a2 0000h external data memory space on-chip code memory space 0000h 4k/2k/1k bytes on-chip code memory unused code memory unused code memory 0fffh 1000h ffffh ffffh page 0 64 bytes page 1 64 bytes fc00h fc3fh fc40h fc7fh nvm data memory area fc00h fc7fh 128 bytes nvm data memory unused data memory config 1 config 2 w79e823/w79e822/w79e 821 memory map bit name function 7~0 nvmaddr.7 ~ nvmaddr.0 the nvm address: the register is indicated nvm data me mory of low byte address on on-chip code memory space. mnemonic: nvmaddr address: c6h
w79e825/824/823a/822a/821a data sheet - 68 - bit name function 7 eer nvm page(n) erase bit. 0: without erase nvm page(n). 1: set this bit to erase nvm data of page(n) to ffh. the nvm has 4 pages and each page have 64 bytes data memory. before se lect page by nvmaddr register that will automatic enable page area, after set this bit, the page will be erased and program counter will halt at this instruction. after finished, program counter will kept next instruction then executed. the nv m page?s address define as below table. 6 ewr nvm data write bit 0: without write nvm data. 1: set this bit to write nvm bytes and progr am counter will halt at this instruction. after write is finished, program counter will kept next instruction then executed . 5~0 - reserved mnemonic: nvmcon address: ceh nvm page(n) area definition table: page start address end address 0 00h 3fh 1 40h 7fh 2 80h bfh 3 c0h ffh note: the w79e823, w79e822 and w79e 821 without page 2 and page 3. bit name function 7~0 nvmdat.7 ~ nvmdat.0 the nvm data write register. the read nvm data is by movc instruction. mnemonic: nvmdata address: cfh
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 69 - revision a2 16. watchdog timer the watchdog timer is a free-running timer which c an be programmed by the user to serve as a system monitor, a time-base generator or an event timer. it is basically a set of dividers that divide the system clock. the divider output is selectable and determines the time -out interval. when the time-out occurs a flag is set, which can cause an interrupt if enabled, and a system reset can also be caused if it is enabled. the interrupt will occur if the i ndividual interrupt enable and the global enable are set. the interrupt and reset functions are independent of each other and may be used separately or together depending on the users software. watchdog timer the watchdog timer should first be restarted by usi ng wdclr. this ensures that the timer starts from a known state. the wdclr bit is used to restart the watchdog timer. this bit is self clearing, i.e. after writing a 1 to this bit the software will autom atically clear it. the watchdog timer will now count clock cycles. the time-out interval is se lected by the two bits wd1 and wd0 (wdcon.5 and wdcon.4). when the selected time-out occurs, t he watchdog interrupt flag wdif (wdcon.3) is set. after the time-out has occurred, the watchdog ti mer waits for an additional 512 clock cycles. if the watchdog reset ewrst (wdcon.1) is enabled, then 512 clocks after the time-out, if there is no wdclr, a system reset due to watchdog timer will o ccur. this will last for two machine cycles, and the watchdog timer reset flag wdrf (wdcon.2) will be set. this indicates to the software that the watchdog was the cause of the reset. when used as a simple timer, the reset and interrupt functions are disabled. the timer will set the wdif flag each time the timer completes the selected time interval. the wdif flag is polled to detect a time-out and the wdclr allows software to restart the timer. the watchdog timer can also be used as a very long timer. the interrupt feature is enabled in this case. every time the time-out occurs an interrupt will occur if the global interrupt enable ea is set. the main use of the watchdog timer is as a system monitor. this is important in real-time control applications. in case of some power glitches or electro-magnetic interference, the processor may begin to execute errant code. if this is left unc hecked the entire system may crash. using the watchdog timer interrupt during software development will allow the user to select ideal watchdog reset locations. the code is first written without the watchdog interrupt or reset. then the watchdog interrupt is enabled to identify code locations wher e interrupt occurs. the user can now insert instructions to reset the watchdog timer, which w ill allow the code to run without any watchdog timer
w79e825/824/823a/822a/821a data sheet - 70 - interrupts. now the watchdog timer reset is enabled and the watchdog interrupt may be disabled. if any errant code is executed now, then the reset wa tchdog timer instructions will not be executed at the required instants and watchdog reset will occur. the watchdog timer time-out selection will result in different time-out values depending on the clock speed. the reset, when enabled, will occurs 512 clocks after the time-out has occurred. time-out values for the watchdog timer wd1 wd0 watchdog interval number of clocks time @ 10 mhz 0 0 2 17 131072 13.11 ms 0 1 2 20 1048576 104.86 ms 1 0 2 23 8388608 838.86 ms 1 1 2 26 67108864 6710.89 ms the watchdog timer will de disabled by a power-on/fail reset. the watchdog timer reset does not disable the watchdog timer, but will restart it. in general , software should restart the timer to put it into a known state. the control bits that support the watchdog timer are discussed below. 16.1 watchdog control wdif: wdcon.3 - watchdog timer interrupt flag. this bit is set whenever the time-out occurs in the watchdog timer. if the watchdog interrupt is enabled (ie1 .4), then an interrupt will occur (if the global interrupt enable is set and other interrupt requirement s are met). software or any reset can clear this bit. wdrf: wdcon.2 - watchdog timer reset flag. this bit is set whenever a watchdog reset occurs. this bit is useful for determined the cause of a reset. software must read it, and clear it manually. a power-fail reset will clear this bit. if ewdrst = 0, then this bit will not be affected by the watchdog timer. ewrst: wdcon.1 - enable watchdog timer reset. this bit when set to 1 will enable the watchdog timer reset function. setting this bit to 0 will dis able the watchdog timer reset function, but will leave the timer running. wdclr: wdcon.0 - reset watchdog timer. this bit is used to clear the watchdog timer and to restart it. this bit is self-clearing, so after the software writes 1 to it t he hardware will automatically clear it. if the watchdog timer reset is enabled, then the wdclr has to be set by the user within 512 clocks of the time-out. if this is not done then a watchdog timer reset will occur.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 71 - revision a2 16.2 clock control of watchdog wd1, wd0: wdcon.5, wdcon.4 - watchdog timer m ode select bits. these two bits select the time-out interval for the watchdog timer. the reset time is 512 clocks longer than the interrupt time-out value. the default watchdog time-out is 2 17 clocks, which is the shortest time-out period. the ewrst, wdif and wdclr bits are protected by the timed a ccess procedure. this prevents software from accidentally enabling or disabling the watchdog timer. more importantly, it makes it highly improbable that errant code can enable or disable the watchdog timer. the security bit wdte is located at bit 7 of config register. this bit is user to configure the clock source of watchdog timer either it is from the internal rc or from the uc clock.
w79e825/824/823a/822a/821a data sheet - 72 - 17. serial port (uart) serial port in the w79e82x series are a full duplex port. the w79e82x series provide the user with additional features such as the frame error dete ction and the automatic address recognition. the serial ports are capable of synchronous as well as asynchronous communication. in synchronous mode the w79e82x series generate the clock and operates in a half duplex mode. in the asynchronous mode, full duplex operation is available. this means that it can simultaneously transmit and receive data. the transmit register and the re ceive buffer are both addressed as sbuf special function register. however any write to sbuf will be to the transmit register, while a read from sbuf will be from the receiver buffer register. the seri al port can operate in four different modes as described below. 17.1 mode 0 this mode provides synchronous communication with external devices. in this mode serial data is transmitted and received on the rxd line. txd is used to transmit the shift clock. the txd clock is provided by the w79e82x series whether the device is transmitting or receiving. this mode is therefore a half duplex mode of seri al communication. in this mode, 8 bits are transmitted or received per frame. the lsb is transmitted/received first. the baud rate is fixed at 1/12 or 1/4 of the oscillator frequency. this baud rate is determined by the sm2 bi t (scon.5). when this bit is set to 0, then the serial port runs at 1/12 of the clock. when set to 1, the serial port runs at 1/4 of the clock. this additional facility of programmable baud rate in mode 0 is the only difference between the standard 8051 and the w79e82x series. the functional block diagram is shown below. data enters and leaves the seri al port on the rxd line. the txd line is used to output the shift clock. the sh ift clock is used to shift data into and out of the w79e82x series and the device at t he other end of the line. any instru ction that causes a write to sbuf will start the transmission. the shift clock will be activated and data will be shifted out on the rxd pin till all 8 bits are transmitted. if sm2 = 1, then the data on rxd will appear 1 clock period before the falling edge of shift clock on txd. the cl ock on txd then remains low for 2 clock periods, and then goes high again. if sm2 = 0, the data on rx d will appear 3 clock periods before the falling edge of shift clock on txd. the cl ock on txd then remains low for 6 clock periods, and then goes high again. this ensures that at the receiving end the data on rxd line c an either be clocked on the rising edge of the shift clock on txd or la tched when the txd clock is low.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 73 - revision a2 1/12 fcpu 0 tx clock rx clock ti ri tx shift rx start rx shift load sbuf shift clock ri ren sm2 clock sin parout sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus sbuf write to sout transmit shift register serial interrupt rxd txd rxd p1.1 alternate input function p1.1 alternate output function p1.0 alternate output function serial port mode 0 1/4 1 serial port mode 0 the ti flag is set high in c1 following the end of trans mission of the last bit. the serial port will receive data when ren is 1 and ri is zero. the shift clock (txd) will be activated and the serial port will latch data on the rising edge of shift clock. the external device should therefore present data on the falling edge on the shift clock. this process continues till a ll the 8 bits have been received. the ri flag is set in c1 following the last rising edge of the shift clo ck on txd. this will stop re ception, till the ri is cleared by software. 17.2 mode 1 in mode 1, the full duplex asynchronous mode is us ed. serial communication frames are made up of 10 bits transmitted on txd and received on rxd. the 10 bi ts consist of a start bit (0), 8 data bits (lsb first), and a stop bit (1). on received, the stop bi t goes into rb8 in the sfr scon. the baud rate in this mode is variable. the serial baud can be progra mmed to be 1/16 or 1/32 of the timer 1 overflow. since the timer 1 can be set to different reload values, a wide variation in baud rates is possible. transmission begins with a write to sbuf. the serial data is brought out on to txd pin at c1 following the first roll-over of divide by 16 counter. the nex t bit is placed on txd pin at c1 following the next rollover of the divide by 16 counter. thus the trans mission is synchronized to the divide by 16 counter and not directly to the write to sbuf signal. after a ll 8 bits of data are transmitted, the stop bit is transmitted. the ti flag is set in the c1 state a fter the stop bit has been put out on txd pin. this will be at the 10th rollover of the divide by 16 counter after a write to sbuf. reception is enabled only if ren is high. the serial por t actually starts the re ceiving of serial data, with the detection of a falling edge on the rxd pin. t he 1-to-0 detector continuously monitors the rxd
w79e825/824/823a/822a/821a data sheet - 74 - line, sampling it at the rate of 16 times the selected baud rate. when a falling edge is detected, the divide by 16 counter is immediately reset. this helps to align the bit boundaries with the rollovers of the divide by 16 counter. the 16 states of the counter effect ively divide the bit time into 16 slices. the bit detection is done on a best of three basis. the bit detector samples the rxd pin, at the 8th, 9th and 10th counter states. by using a majority 2 of 3 voting system, the bit val ue is selected. this is done to improve the noise rejection feature of the serial port. if the first bit detected after the falling edge of rxd pin is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. the serial port again looks for a falling edge in the rxd line. if a valid start bit is detected, then the rest of the bits are also detected and shifted into the sbuf. after shifting in 8 data bits, there is one more shift to do, after which the sbuf and rb8 are loaded and ri is set. however certain conditions must be met before the loading and setting of ri can be done. 1. ri must be 0 and 2. either sm2 = 0, or the received stop bit = 1. if these conditions are met, then the stop bit goes to rb8, the 8 data bits go into sbuf and ri is set. otherwise the received frame may be lost. after the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the rxd pin. 1/2 1/16 tx clock rx clock ti ri tx shift rx start rx shift load sbuf smod clock sin d8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus sbuf write to sout transmit shift register serial interrupt txd rxd serial port mode 1 parout rb8 start stop 0 1 bit detector 1-to-0 detector sample 1/16 0 timer 1 overflow 1 receive shift register serial port mode 1
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 75 - revision a2 17.3 mode 2 this mode uses a total of 11 bits in asynch ronous full-duplex communication. the functional description is shown in the figure below. the frame cons ists of one start bit (0), 8 data bits (lsb first), a programmable 9th bit (tb8) and a stop bit (0). the 9t h bit received is put into rb8. the baud rate is programmable to 1/32 or 1/64 of the oscillator fr equency, which is determined by the smod bit in pcon sfr. transmission begins with a write to sbuf. the serial data is brought out on to txd pin at c1 following the first roll-over of the divide by 16 counter. the next bit is placed on txd pin at c1 following the next rollover of the divide by 16 count er. thus the transmission is synchronized to the divide by 16 counter, and not directly to the writ e to sbuf signal. after all 9 bits of data are transmitted, the stop bit is transmitted. the ti flag is set in the c1 state after the stop bit has been put out on txd pin. this will be at the 11th rollover of the divide by 16 counter after a write to sbuf. reception is enabled only if ren is high. the serial por t actually starts the re ceiving of serial data, with the detection of a falling edge on the rxd pin. t he 1-to-0 detector continuously monitors the rxd line, sampling it at the rate of 16 times the selected baud rate. when a falling edge is detected, the divide by 16 counter is immediately reset. this helps to align the bit boundaries with the rollovers of the divide by 16 counter. the 16 states of the counter effectively divide the bit time into 16 slices. the bit detection is done on a best of three bases. the bit detector samples the rxd pin, at the 8th, 9th and 10th counter states. by using a ma jority 2 of 3 voting system, the bit value is selected. this is done to improve the noise rejecti on feature of the serial port. 1/2 1/16 tx clock rx clock ti ri tx shift rx start rx shift load sbuf smod clock sin d8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus sbuf write to sout transmit shift register serial interrupt txd rxd serial port mode 2 parout rb8 start stop 0 1 bit detector 1-to-0 detector sample 1/16 0 clock/2 1 d8 tb8 receive shift register serial port mode 2
w79e825/824/823a/822a/821a data sheet - 76 - if the first bit detected after the falling edge of rxd pin, is not 0, then this indicates an invalid start bit, and the reception is immediately aborted. the serial port again looks for a falling edge in the rxd line. if a valid start bit is detected, then the rest of t he bits are also detected and shifted into the sbuf. after shifting in 9 data bits, there is one more shift to do, after which the sbuf and rb8 are loaded and ri is set. however certain conditions must be met before the loading and setting of ri can be done. 1. ri must be 0 and 2. either sm2 = 0, or the received stop bit = 1. if these conditions are met, then the stop bit goes to rb8, the 8 data bits go into sbuf and ri is set. otherwise the received frame may be lost. after the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the rxd pin. 17.4 mode 3 this mode is similar to mode 2 in all respects, ex cept that the baud rate is programmable. the user must first initialize the serial related sfr scon before any communication can take place. this involves selection of the mode and baud rate. the ti mer 1 should also be initialized if modes 1 and 3 are used. in all four modes, transmission is started by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by t he condition ri = 0 and ren = 1. this will generate a clock on the txd pin and shift in 8 bits on the rxd pin. reception is initiated in the other modes by the incoming start bit if ren = 1. the external device will start the communication by transmitting the start bit. 1/2 1/16 tx clock rx clock ti ri tx shift rx start rx shift load sbuf smod clock sin d8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus sbuf write to sout transmit shift register serial interrupt txd rxd serial port mode 3 parout rb8 start stop 0 1 bit detector 1-to-0 detector sample 1/16 0 1 d8 tb8 timer 1 overflow receive shift register serial port mode 3
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 77 - revision a2 serial ports modes sm0 sm1 mode type baud clock frame size start bit stop bit 9th bit function 0 0 0 synch. 4 or 12 tclks 8 bits no no none 0 1 1 asynch. timer 1 or 2 10 bits 1 1 none 1 0 2 asynch. 32 or 64 tclks 11 bits 1 1 0, 1 1 1 3 asynch. timer 1 or 2 11 bits 1 1 0, 1 17.5 framing error detection a frame error occurs when a valid stop bit is not det ected. this could indicate incorrect serial data communication. typically the frame error is due to noise and contention on the serial communication line. the w79e82x series have the facility to detec t such framing errors and set a flag which can be checked by software. the frame error fe bit is located in scon.7. th is bit is normally used as sm0 in the standard 8051 family. however, in the w79e82x series it serv es a dual function and is called sm0/fe. there are actually two separate flags, one for sm0 and the other for fe. the flag that is actually accessed as scon.7 is determined by smod0 (pcon.6) bit. w hen smod0 is set to 1, then the fe flag is indicated in sm0/fe. when smod0 is set to 0, then the sm0 flag is indicated in sm0/fe. the fe bit is set to 1 by hardware but must be cl eared by software. note that smod0 must be 1 while reading or writing to fe. if fe is set, then any follo wing frames received without any error will not clear the fe flag. the clearing has to be done by software. 17.6 multiprocessor communications multiprocessor communications makes use of the 9th data bit in modes 2 and 3. in the w79e82x series, the ri flag is set only if the received byte corresponds to the given or broadcast address. this hardware feature eliminates the software overhead required in checking every received address, and greatly simplifies the software programmer task. in the multiprocessor communication mode, the addr ess bytes are distinguis hed from the data bytes by transmitting the address with the 9th bit set high. when the master processor wants to transmit a block of data to one of the slaves, it first sends out the address of the target ed slave (or slaves). all the slave processors should have their sm2 bit set high when waiting for an address byte. this ensures that they will be interrupted only by the reception of a address byte. the automatic address recognition feature ensures that only the address ed slave will be interrupted. the address comparison is done in hardware not software. the addressed slave clears the sm2 bit, thereby clear ing the way to receive data bytes. with sm2 = 0, the slave will be interrupted on the reception of every single complete frame of data. the unaddressed slaves will be unaffected, as they will be st ill waiting for their address. in mode 1, the 9th
w79e825/824/823a/822a/821a data sheet - 78 - bit is the stop bit, which is 1 in case of a valid frame. if sm2 is 1, then ri is set only if a valid frame is received and the received byte matches the given or broadcast address. the master processor can selectively communicate wi th groups of slaves by using the given address. all the slaves can be addressed together using t he broadcast address. the addresses for each slave are defined by the saddr and saden sfrs. the slav e address is an 8-bit value specified in the saddr sfr. the saden sfr is actually a mask for the byte value in saddr. if a bit position in saden is 0, then the corresponding bit position in saddr is don't care. only those bit positions in saddr whose corresponding bits in saden are 1 are used to obtain the given address. this gives the user flexibility to address multiple slav es without changing the slave address in saddr. the following example shows how the user can defi ne the given address to address different slaves. slave 1: saddr 1010 0100 saden 1111 1010 given 1010 0x0x slave 2: saddr 1010 0111 saden 1111 1001 given 1010 0xx1 the given address for slave 1 and 2 differ in the lsb. fo r slave 1, it is a don't care, while for slave 2 it is 1. thus to communicate only with slave 1, the master must send an address with lsb = 0 (1010 0000). similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. hence to communicate only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). if the master wishes to communicate with both slaves simult aneously, then the address must have bit 0 = 1 and bit 1 = 0. the bit 3 position is don't care for both the sl aves. this allows two different addresses to select both slaves (1010 0001 and 1010 0101). the master can communicate with all the slaves simultaneously with the broadcast address. this address is formed from the logical or of the sa ddr and saden sfrs. the zeros in the result are defined as don't cares in most cases the broadcas t address is ffh. in the previous case, the broadcast address is (1111111x) for slave 1 and (11111111) for slave 2. the saddr and saden sfrs are located at address a9h and b9h respectively. on reset, these two sfrs are initialized to 00h. this results in given address and broadcast address being set as xxxx xxxx(i.e. all bits don't care). this effectively re moves the multiprocessor communications feature, since any selectivity is disabled.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 79 - revision a2 18. timed access protection the w79e82x series have a new feature, like t he watchdog timer which is a crucial to proper operation of the system. if left unprotected, err ant code may write to the watchdog control bits resulting in incorrect operation and lo ss of control. in order to prev ent this, the w79e82x series have a protection scheme which controls the write access to critical bits. this protection scheme is done using a timed access. in this method, the bits which are to be prot ected have a timed write enable window. a write is successful only if this window is active, otherwise the write will be discarded. this write enable window is open for 3 machine cycles if certain conditions are met. after 3 machine cycles, this window automatically closes. the window is opened by writing aah and immediately 55h to the timed access(ta) sfr. this sfr is located at addr ess c7h. the suggested code for opening the timed access window is ta reg 0c7h ;define new register ta, located at 0c7h mov ta, #0aah mov ta, #055h when the software writes aah to the ta sfr, a count er is started. this counter waits for 3 machine cycles looking for a write of 55h to ta. if the second write (55h) occurs within 3 machine cycles of the first write (aah), then the timed access window is opened. it remains open for 3 machine cycles, during which the user may write to the protected bits. once the window closes the procedure must be repeated to access the other protected bits. examples of timed assessing are shown below. example 1: valid access mov ta, #0aah ;3 m/c note: m/c = machine cycles mov ta, #055h ;3 m/c mov wdcon, #00h ;3 m/c example 2: valid access mov ta, #0aah ;3 m/c mov ta, #055h ;3 m/c nop ;1 m/c setb ewrst ;2 m/c example 3: valid access mov ta, #0aah ;3 m/c mov ta, #055h ;3 m/c orl wdcon, #00000010b ;3m/c example 4: invalid access mov ta, #0aah ;3 m/c
w79e825/824/823a/822a/821a data sheet - 80 - mov ta, #055h ;3 m/c nop ;1 m/c nop ;1 m/c clr ewt ;2 m/c example 5: invalid access mov ta, #0aah ;3 m/c nop ;1 m/c mov ta, #055h ;3 m/c setb ewt ;2 m/c in the first three examples, the writing to the protected bits is done before the 3 machine cycles window closes. in example 4, however, the writing to the protected bit occurs after the window has closed, and so there is effectively no change in the status of the protected bit. in example 5, the second write to ta occurs 4 machine cycles after t he first write, therefore the timed access window is not opened at all, and the write to the protected bit fails.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 81 - revision a2 19. keyboard interrupt (kbi) the w79e82x series are provided 8 keyboard interrupt function to detect keypad status which key is acted, and allow a single interrupt to be generated when any key is pressed on a keyboard or keypad connected to specific pins of t he w79e82x series, as shown below figure. this interrupt may be used to wake up the cpu from idle or power down modes , after chip is in power down or idle mode. to support keyboard function is by port 0. it can allo w any or all pins of port 0 to be enabled to cause this interrupt. port pins are enabled by the setting of bits of kbi0 ~ kbi7 in the kbi register, as shown below figure. the keyboard interrupt flag (kbf) in the auxr1 register is set when any enabled pin is pulled low while the kbi interrupt function is ac tive, and the low pulse must more than 1 machine cycle, an interrupt will be generated if it has been enabled. the kbf bit set by hardware and must be cleared by software. in order to determine which ke y was pressed, the kbi will allow the interrupt service routine to poll port 0. p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.0 kbi.0 kbi.1 p0.1 kbi.2 kbi.3 kbi.4 kbi.5 kbi.6 kbi.7 ekb (from ie1 register) kbf (kbi interrupt)
w79e825/824/823a/822a/821a data sheet - 82 - 20. analog comparators the w79e82x series are provided two comparator s. input and output opti ons allow use of the comparators in a number of different configurati ons. the comparator output is a logical one when its positive input is greater than its negative input, otherwise the output is a zero. each comparator can be configured to cause to an interrupt when the out put value change. the block diagram is as below. each comparator has a control register (cmp1 and cmp2), both inputs are cinna, cinnb, cmpref and internal reference voltage, and outputs are cmp1 and cmp2 by setting oen bit. after enable comparators the comparator need waited stable ti me to guarantee comparator output. if programmer used internal reference voltage, it will be set oen bi t to ?1?. the value of internal reference voltage (vref) is 1.28v +/- 10%. - + cmf1 cmp1(p0.6) interrupt cn1 cp1 vref co1 oe1 change detect comparator1 (p0.4) cin1a (p0.3) cin1b (p0.5) cmpref - + cmf2 cmp2(p0.0) interrupt cn2 cp2 co2 oe2 change detect comparator2 (p0.2) cin2a (p0.1) cin2b cmp1 analog circuit cmp2 analog circuit vref ce1 ce2 enable cmp1 enable cmp2 en
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 83 - revision a2 21. i/o port configuration the w79e82x series have three i/o ports, port 0, port 1 and port 2. all pins of i/o ports can be configured to one of four types by software except p1.5 is only i nput pin. when p1.5 is configured reset pin by rpd=0 in the config 1 register, the w79e82x series can support 15 pins by use crystal. if used on-chip rc oscillator the p1.5 is configured input pin, t he w79e82x series can be supported up to 18 pins. the i/o ports c onfiguration setting as below table. i/o port configuration table pxm1.y pxm2.y port input/output mode 0 0 quasi-bidirectional 0 1 push-pull 1 0 input only (high impedance) 1 1 open drain all port pins can be determined to high or low afte r reset by configure prhi bit in the config1 register. after reset, these pins are in quasi-bidirect ional mode. the port pin of p1.5 only is a schmitt trigger input. enabled toggle outputs from timer 0 and timer 1 by ent0 and ent1 on p2m1 register, the output frequency of timer 0 or timer 1 is by timer overflow. each i/o port of the w79e82x series may be select ed to use ttl level inputs or schmitt inputs by p(n)s bit on p2m1 register, where n is 0, 1 or 2. when p(n)s is set to 1, ports are selected schmitt trigger inputs on port(n). the p2.0(xtal2) can be configured clock output when used on-chip rc or external oscillator is clock source, and the frequenc y of clock output is divided by 4 on on-chip rc clock or external oscillator. 21.1 quasi-bidirectional output configuration after chip was power on or reset, the all ports out put are this mode, and output is common with the 8051. this mode can be used as both an input and out put without the need to reconfigure the port. when the pin is pulled low, it is driven strongly and abl e to sink a fairly large current. these features are somewhat similar to an open drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. this mode has three pull-up resisters that are ?s trong? pull-up, ?weak? pull-up and ?very weak? pull-up. the ?strong? pull-up is used fast transition from logi c ?0? change to logic ?1?, and it is fast latch and transition. when port pins is occur from logic ?0? to logic ?1?, the strong pull-up will quickly turn on two cpu clocks to pull high then turn off. the ?weak? pull-up is turned on when the input port pin is logic ?1? level or itself is logic ?1?, and it provides the most source current for a quasi-bidirectional pin that output is ?1? or port latch is logic ?0??.
w79e825/824/823a/822a/821a data sheet - 84 - the ?very weak? pull-up is turned on when the port latch is logic ?1?. if port latch is logic ?0?, it will be turned off. the very weak pull-up is support a very sma ll current that will pull the pin high if it is left floating. and the quasi-bidirectional port c onfiguration is shown as below figure. if port pin is low, it can drives large sink curr ent for output, and it is similar with push-pull and open drain on sink current output. quasi-bidirection output port pin 2 cpu clock delay input data port latch data pp p n vdd strong very weak weak 21.2 open drain output configuration to configure this mode is turned off all pull-ups. if used similar as a logic output, the port must has an external pull-up resister. the open drain port configuration is shown as below. open drain output port pin port latch data n input data
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 85 - revision a2 21.3 push-pull output configuration the push-pull output mode has two strong pull-up and pull-down structure that support large source and sink current output. it remove ?weak? pull-up and ?very weak? pull-up resister and remain ?strong pull-up resister on quasi-bidirecti onal output mode. the ?strong? pull-up is always turns on when port latch is logic ?1? to support source current. the push- pull port configuration is shown in below figure. the w79e82x series have three port pins that c an?t be configured are p1.2, p1.3, and p1.5. the port pins p1.2 and p1.3 are configured to open drain out puts. they may be used as inputs by writing ones to their respective port latches. push-pull output port pin input data port latch data p n vdd 21.4 input only configuration by configure this mode, the ports are only digital input and disable digital output. the w79e82x series can select input pin to schmitt trigger or ttl level input by pxm1.y and pxm2.y registers.
w79e825/824/823a/822a/821a data sheet - 86 - 22. oscillator the w79e82x series provides three oscillator input option. these are configured at config register (config1) that include on-chip rc oscillator op tion, external clock input option and crystal oscillator input option. the crystal oscillato r input frequency may be supported from 4mhz to 20mhz, and without capacitor or resister. fosc0 fosc1 00h 11h 10h crystal oscillator external clock input internal rc oscillator 16 bits ripple counter divide-by-m (divm register) cpu clock power monitor reset power down 1/4 adcclk peripheral clock 22.1 on-chip rc oscillator option the on-chip rc oscillator is fixed at 6mhz +/- 25% frequency to support clock source. when fosc1, fosc0 = 10h, the on-chip rc oscillator is enabled. a clock output on p2.0 (xtal2) may be enabled when on-chip rc oscillator is used. 22.2 external clock input option the clock source pin (xtal1) is form external clock input by fosc1, fosc0 = 11h, and frequency range is form 0hz up to 20mhz. a clock output on p2.0 (xtal2) may be enabled when external clock input is used. the w79e82x series supports a clock output functi on when either the on-chip rc oscillator or the external clock input options is selected. this allo ws external devices to sy nchronize to the w79e82x serial. when enabled, via the enclk bit in the p2m1 register, the clock output appears on the xtal2/clkout pin whenever the on-chip oscillator is running, including in idle mode. the frequency of the clock output is 1/4 of the cpu clock rate. if the clock output is not needed in idle mode, it may be turned off prior to entering idle mode, saving additional power. the clock output may also be enabled when the external clock input option is selected.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 87 - revision a2 22.3 cpu clock rate select the cpu clock of w79e82x series may be selected by the divm register. if divm = 00h, the cpu clock is running at 4 cpu clock pr e machine cycle, and without any di vision from source clock (fosc). when the divm register is set to n value, the cpu clock is divided by 2( dvim+1), so cpu clock frequency division is from 4 to 512. t he user may use this feature to set cpu at a lower speed rate for reducing power consumption. this is very similar to the situation when cpu has entered idle mode. in addition this frequency division function affect all peri pheral timings as they are all sourcing from the cpu clock(fcpu). 23. power monitoring function power-on detect and brownout are two additional power monitoring functions implemented in w79e82x to prevent incorrect operation during power up and power drop or loss. 23.1 power on detect the power?on detect function is a designed to detect power up after power voltage reaches to a level where brownout detect can work. after power on detect, the por (pcon.4) will be set to ?1? to indicate an initial power up condition. the por flag will be cleared by software. 23.2 brownout detect the brownout detect function is detect power volt age is drops to brownout voltage level, and allows preventing some process work or indicate power warming. the w79e82x series have two brownout voltage levels to select by bov (config1.4). if bo v =0 that brownout voltage level is 3.8v, if bov = 1 that brownout voltage level is 2.5v. when the brow nout voltage is drop to select level, the brownout detector will detect and keeps this active until vdd is returns to above brownout detect voltage. the brownout detect block is as follow. drownout detect block boi (enable brownout detect) brownout detect circuit 0 1 bof to reset to brownout interrupt bod when brownout detect is enabled by bod (auxr1.6), the bof (pcon.5) flag will be set that it cause brownout reset or interrupt, and bof will be cleared by software. if boi (auxr1.5) is set to ?1?, the brownout detect will cause interrupt via t he ea (ie.7) and ebo (ie.5) bits is set. in order to guarantee a correct detection of br ownout, the vdd fail time must be slower than 50mv/us, and rise time is slower t han 2mv/us to ensure a proper reset.
w79e825/824/823a/822a/821a data sheet - 88 - 24. pulse width modulated outputs (pwm) the w79e82x series have four/two -channels pulse width modulated (pwm), and the pwm outputs are pwm0(p0.1), pwm1(p1.6), pwm2(p1.7) and pwm3(p 0.0). when prhi is set to ?1?, after chip reset, the internal output of the each pwm channels are ?1?. when prhi is set to ?0?, after chip reset, the internal output of the each pwm channels are ?0?. so, in the case, if pwm output pins will output ?1?, it must be written a ?1? to each pwm pins to high state. a block diagram is shown as below figure. the w79e82x series support 10-bits down counter whic h clock source of counter is use the internal microcontroller clock as its input. the pwm count er clock, has the same frequency as the clock source f cpu = f osc . when the counter reaches underflow it will automatic reloaded from counter register. the pwm frequency is given by: f pwm = f cpu / (pwmp+1), where pwmp is 10-bits register of pwmph.1, pwmph.0 and pwmpl.7~pwmpl.0. when pwmp register is written, it will automatically load by pwm run, load and cf is ?1?, where cf flag is 10-bits down counter reac hes underflow, the cf flag will autom atic clear by next cycle. when pwmp register was load to counter register, the l oad bit will automatically cl ear by next cycle. if the first pwm output cycle is correct by pwmp setting, it will be clear by clrpwm to clear 10-bits counter to 000h, then set pwmrun and load bits to run pwm. the pulse width of each pwm output is determi ned by the compare registers of pwm0l through pwm3l and pwm0h through pwm3h. when pwm compare register is greater than 10-bits counter register, the pwm output is low. if want to change out put width of pwm, after writer pwmn register, must set load bit to ?1? then will be loaded to co mpare register by next underflow. the pwm output high pulses width is given by: t hi = (pwmp ? pwmn+1). notice, if compare register is set to 000h, the pwmn output is high, and if compare register is set to 3 ffh, the pwmn output is low.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 89 - revision a2 10-bits counter compare register counter register pwm0 register pwmrun f cpu + - compare register pwm1 register + - compare register pwm2 register + - compare register pwm3 register + - pwm1i pwm2i pwm3i pwm0i pwm0b pwm1b pwm2b pwm3b pwm2 (p1.7) pwm3 (p0.0) pwm1 (p1.6) pwm0 (p0.1) 0 1 0 0 0 1 1 1 + - cf x x x x y y y y > > > > load pwmp register bken brake control block bpen bkch clrpwm clear counter bkps brake pin (p0.2) bkf 0 1 brake flag enable external brake pin (bpen,bkch) = (1,0) p0.2=0 p0.2=1 w79e825/w79e824 pwm block diagram
w79e825/824/823a/822a/821a data sheet - 90 - 10-bits counter compare register counter register pwm0 register pwmrun fosc + - compare register pwm1 register + - pwm1i pwm0i pwm0b pwm1b pwm1 (p1.6) pwm0 (p0.1) 0 1 0 1 + - cf x x y y > > load pwmp register bken break control block bpen bkps bkch clrpwm clear counter brake pin (p0.2) bkf 0 1 brake flag enable external brake pin (bpen,bkch) = (1,0) p0.2=0 p0.2=1 w79e823/w79e822/w79e821 pwm block diagram the all pwm control registers are pwmcon1, pwmcon2, and pwmcon3 register, and function description as below. pwm counter low bits regi ster pwmpl(d9h) bit name function 7~0 pwmp.7 ~pwmp.0 pwm counter low bit 7~0 register pwm counter high bits register pwmph(d1h) bit name function 7~2 - reserved 1~0 pwmp.9 ~pwmp.8 pwm counter high bit 9~8 register
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 91 - revision a2 pwm 0 low bits register pwm0l(dah) bit name function 7~0 pwm0.7 ~pwm0.0 pwm 0 low bit 7~0 register pwm 1 low bits register pwm1l(dbh) bit name function 7~0 pwm1.7 ~pwm1.0 pwm 1 low bit 7~0 register pwm 2 low bits register pwm2l(ddh) bit name function 7~0 pwm2.7 ~pwm2.0 pwm 2 low bit 7~0 register note: the w79e823, w79e822 and w 79e821 without pwm2l register. pwm 3 low bits register pwm3l(deh) bit name function 7~0 pwm3.7 ~pwm3.0 pwm3 low bit 7~0 register note: the w79e823, w79e822 and w 79e821 without pwm3l register. pwm 0 high bits register pwm0h(d2h) bit name function 7~2 - reserved 1~0 pwm0.9 ~pwm0.8 pwm 0 high bit 9~8 register pwm 1 high bits register pwm1h(d3h) bit name function 7~2 - reserved 1~0 pwm1.9 ~pwm1.8 pwm 1 high bit 9~8 register
w79e825/824/823a/822a/821a data sheet - 92 - pwm 2 high bits register pwm2h(d5h) bit name function 7~2 - reserved 1~0 pwm2.9 ~pwm2.8 pwm 2 high bit 9~8 register note: the w79e823, w79e822 and w 79e821 without pwm2h register. pwm 3 high bits register pwm3h(d6h) bit name function 7~2 - reserved 1~0 pwm3.9 ~pwm3.8 pwm 3 high bit 9~8 register note: the w79e823, w79e822 and w 79e821 without pwm3h register. pwm control register 1 pwmcon1(dch) bit name function 7 pwmrun 0: the pwm is not running. 1: the pwm counter is running. 6 load 0: the registers value of pwmp and pwmn is without loaded to counter and compare registers. 1: the pwmp and pwmn registers load val ue to counter and compare registers at the counter underflow. this bit is automat ically cleared by hardware after the pwmp and pwmn are transferred to c ounter and compare register. 5 cf 10-bit counter overflow flag: 0: the 10-bit counter down count is not overflow. 1: the 10-bit counter down count is ov erflow. it will be cleared by software. 4 clrpwm 1: clear 10-bit pwm counter to 000h. the bi t will automatically cleared by next cycle. 3 pwm3i 0: pwm3 out is non-inverted. 1: pwm3 output is inverted. 2 pwm2i 0: pwm2 out is non-inverted. 1: pwm2 output is inverted. 1 pwm1i 0: pwm1 out is non-inverted. 1: pwm1 output is inverted. 0 pwm0i 0: pwm0 out is non-inverted. 1: pwm0 output is inverted. note: the w79e823, w79e822 and w79e821 wi thout pwm2i and pwm3i bit control.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 93 - revision a2 pwm control register 2 pwmcon2(dfh) bit name function 7 bkch see the below table, when bken is set. 6 bkps 0: brake is asserted if p0.2 is low. 1: brake is asserted if p0.2 is high 5 bpen see the below table, when bken is set. 4 bken 0: the brake is never asserted. 1: the brake is enabled, and see the below table. 3 pwm3b 0: the pwm3 output is low, when brake is asserted. 1: the pwm3 output is high, when brake is asserted. 2 pwm2b 0: the pwm2 output is low, when brake is asserted. 1: the pwm2 output is high, when brake is asserted. 1 pwm1b 0: the pwm1 output is low, when brake is asserted. 1: the pwm1 output is high, when brake is asserted. 0 pwm0b 0: the pwm0 output is low, when brake is asserted. 1: the pwm0 output is high, when brake is asserted. note: the w79e823, w79e822 and w79e821 wi thout pwm2b and pwm3b bit control. brake condition table bpen bkch break condition 0 0 brake on, software brake 0 1 on, when pwm is not running, the pw m output condition is follow pwmnb setting. 1 0 on, when brake pin asserted, no pwm output, the bkf will be set and pwmrun will be cleared. 1 1 no any active. pwm control register 3 pwmcon3(d7h) bit name function 7~1 - reserved 0 bkf the external brake pin flag. 0: the pwm is not brake. 1: the pwm is brake by external brake pi n. it will be cleared by software. if this bit is set, pwmrun can?t be set.
w79e825/824/823a/822a/821a data sheet - 94 - the w79e82x series chips have support brake function by software or external pin(p0.2). that brake control is by pwmcon2 register. the software br ake and external pin brake setting as refer brake condition table. when brake is asserted, the pw m outputs are by pwmnb setting. by the software brake, the bken is set to ?1? that will enable brake function and determined by bpen and bkch bits. the (bpen, bkch) = (0,0), brake is asserted. the (bpen, bkch) = (0,1), the pwm outputs are follow pwmrun bit; when pwm is not running that mean is pwmrun = 0, the pwm outputs are asserted by pwmnb setting; when pwm is running, the pwmrun = 1, and keeping pwm outputs. by the external brake pin(p0.2) brake, w79e82x se ries chips have brake interrupt service or polling brake flag (bkf) if external pin is asserted. if to decide p0.2 is low is asserted by bkps = 0, the bkf(pwmcon3.0) will be set to ?1? and pwnrun will be cleared to stop pwm run, the pwm outputs condition are by pwmnb setting. a fter brake pin is release, since the brake pin being asserted will automatic ally clear the run bit and bkf(pwmcon3.0) flag will be set, pwmcon1.7, the user program can po ll this bit or enable pwm?s brake interrupt to determine when the brake pin causes a brake to occur. the other method for detecting a brake caused by the brake pin would be to tie the brake pin to one of the external interrupt pins. this latter approach is needed if the brake signal can be of insuffi cient length to ensure that it can be captured by a polling routine. when, after being asserted, t he condition causing the brake is removed, the pwm outputs go to whatever stat e that had immediately prior to the brak e. this means that in order to go from brake being asserted to having the pwm run without going through an indeterminate state care must be taken. if the in order to smoothly release brake by external br ake pin is asserted then pwm is going to run, the step interval as refer below figure.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 95 - revision a2 to change external pin to s/w brake to set pwm comparator output to high (1) or low (0), the output high is 000h, output low is 3ffh or given output brake pattern to clear bkf flag, that will release pwmnb brake clear 10-bits counter to 000h by clrpwm bit start pwm running, that set pwmrun and load to 1 . polling external brake pin. if brake pin is not active yes no to decide pwm output frequency and width by pwmp and pwm[3:0] registers start end
w79e825/824/823a/822a/821a data sheet - 96 - 25. analog-to-digital converter the adc contains a dac which converts the cont ents of a successive approx imation register to a voltage (vdac) which is compared to the analog input voltage (vin). the output of the comparator is fed to the successive approximation control logi c which controls the successive approximation register. a conversion is initiated by setting a dcs in the adcon regist er. adcs can be set by software only or by either hardware or software. the software only start mode is selected when cont rol bit adcon.5 (adcex) =0. a conversion is then started by setting control bi t adcon.3 (adcs ) the hardware or software start mode is selected when adcon.5 =1, and a conversion may be started by setting adcon.3 as above or by applying a rising edge to external pin stadc. when a conversi on is started by applying a rising edge, a low level must be applied to stadc for at least one machine cycle followed by a high level for at least one machine cycle. the low-to-high transition of stadc is recognized at the end of a machine cycle, and the conversion commences at the beginning of the next cycle. when a conversion is initiated by software, the conversion starts at the beginning of the machine cycle which follows the instruction that sets adcs. adcs is actually implemented with tpw flip-fl ops: a command flip-flop which is affected by set operations, and a status flag which is accessed during read operations. the next two machine cycles are used to initiate the converter. at the end of t he first cycle, the adcs status flag is set end a value of ?1? will be returned if the adcs flag is read while the conversion is in progress. sampling of the analog input comm ences at the end of the second cycle. during the next eight machine cycles , the voltage at the previously se lected pin of port 5 is sampled, and this input voltage should be stable in order to obtain a useful sample. in any event, the input voltage slew rate must be less than 10v/ms in order to prevent an undefined result. the successive approximation control logic first sets t he most significant bit and clears all other bits in the successive approximation register (10 0000 0000b) . the output of the dac (50% full scale) is compared to the input voltage vin. if the input volt age is greater than vdac, then the bit remains set; otherwise if is cleared. the successive approximation control logic now se ts the next most significant bit (11 0000 0000b or 01 0000 0000b, depending on the previous result), and t he vdac is compared to vin again. if the input voltage is greater then vdac, then the bit remain s set; otherwise it is cleared. this process is repeated until all ten bits have been test ed, at which stage the result of the conversion is held in the successive approximation register. the conver sion takes four machine cycles per bit. the end of the 10-bit conversion is flagged by contro l bit adcon.4 (adci). the upper 8 bits of the result are held in special function register adch, and the two remaining bits are held in adcon.7 (adc.1) and adcon.6 (adc.0). the user may ignore t he two least significant bits in adcon and use the adc as an 8-bit converter (8 upper bits in adch). in any event, the total actual conversion time is 50 machine cycles. adc will be set and the adcs status flag will be rese t 50 cycles after the adcs is set. control bits adcon.0 and adcon.2 are used to control an analog multiplexer which selects one
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 97 - revision a2 of 4 analog channels. an adc conversion in progre ss is unaffected by an external or software adc start. the result of a completed conversion rema ins unaffected provided adci = logic 1; a new adc conversion already in progress is aborted when the id le or power down mode is entered. the result of a completed conversion (adci = logic 1) re mains unaffected when entering the idle mode. dac msb lsb successive approximation register vin + - comparator start ready (stop) the successive approximation adc successive approximation control logic v dac successive approximation adc 25.1 adc resolution and analog supply: the adc circuit has its own supply pins (av dd and avss) and one pins (vref+) connected to each end of the dac?s resistance-l adder that the avdd and vref+ are connected to vdd and avss is connected to vss. the ladder has 1023 equally spaced taps, separated by a resistance of ?r?. the first tap is located 0.5r above avss, and the last tap is located 0.5r below vref+. this gives a total ladder resistance of 1024r. this structure ensur es that the dac is m onotonic and results in a symmetrical quantization error. for input voltages between avss and [(vref+) + ? lsb ], the 10-bit result of an a/d conversion will be 0000000000b = 000h. for input voltages between [(vref+) ? 3/2 lsb] and vref+, the result of a conversion will be 1111111111b = 3ffh. avref+ and avss may be between avdd + 0.2v and avss ? 0.2 v. avref+ should be positive with res pect to avss, and the input voltage (vin ) should be between avref+ and avss. the result can always be calculated from the following formula: result = avref vin 1024 + or result = vss vdd 1024
w79e825/824/823a/822a/821a data sheet - 98 - 10-bits adc block adc0(p0.3) adc[9:0] adci adcs vdd vref+ vss aadr[1:0] analog input multiplexer 0 1 p1.4 adcex adcclk adc block daigram adc conversion block adcen adc1(p0.4) adc2(p0.5) adc3(p0.6) avss avdd the adc block diagram
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 99 - revision a2 26. i2c serial control the i2c bus uses two wires (sda and scl) to tr ansfer information between devices connected to the bus. the main features of the bus are: ? bidirectional data transfe r between masters and slaves ? multimaster bus (no central master) ? arbitration between simultaneously transmitting master s without corruption of serial data on the bus ? serial clock synchronization allows devices with di fferent bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? the i2c bus may be used for test and diagnostic purposes the output latches of p1.2 and p1.3 must be set to logic 1 in order to enable sio1. the w79e82x series on-chip i2c logic provide a seri al interface that meets the i2c bus specification and supports all transfer modes (other than the lo w-speed mode) from and to the i2c bus. the i2c logic handles bytes transfer autonomously. it also keeps tr ack of serial transfers, via a status register (i2status) which reflects the status of the i2c bus. the cpu interfaces to the i2c logic via the follo wing four special function registers: i2con (sio1 control register), i2status (sio 1 status register), i2dat (sio 1 data register), and i2adr (sio1 slave address register). the sio1 logic interfaces to the external i2c bus via two port 1 pins: p1.2/scl (serial clock line) and p1.3/sda (serial data line). 26.1 sio1 port the sio1 port is a serial i/o port, which supports all transfer modes from and to the i2c bus. the sio1 port handles byte transfers autonomously. to enable this port, the bit ens1 in i2con should be set to '1'. the cpu interfaces to the sio1 port through the following six special function registers: i2con (control register, c0h), i2status (status register, bdh), i2dat (data register, bch), i2addr (address registers, c1h), i2clk (clock rate register beh) and i2timer (timer counter register, bfh). the sio1 h/w interfaces to the i2c bus via two pins: sda (p1.3, serial data line) and scl (p1.2, serial clock line). the output latches of p1.2 and p1.3 must be set to "1" before using this port. 26.2 the i2c control registers: the w79e82x series need set some control register s to control i2c serial port. please reference detail description is shown below. 26.2.1 the address registers, i2addr the sio1 is equipped with a address registers: i2a ddr. the cpu can read from and write to an 8-bit, directly addressable sfrs. the cont ent of these registers are irrele vant when sio1 is in master modes. in the slave modes, the seven most signi ficant bits must be loaded with the mcu's own address. the sio1 hardware will react if either of the addresses is matched.
w79e825/824/823a/822a/821a data sheet - 100 - bit: 7 6 5 4 3 2 1 0 i2addr.7 i2addr.6 i2addr.5 i2a ddr.4 i2addr.3 i2addr.2 i2addr.1 gc mnemonic: i2addr address: c1h 26.2.2 the data register, i2dat this register contains a byte of serial data to be transmitted or a byte which has just been received. the cpu can read from or write to this 8-bit directly addressable sfr while it is not in the process of shifting a byte. this occurs when sio1 is in a defined state and the serial interrupt flag (si) is set. data in i2dat remains stable as long as si bit is se t. while data is being shifted out, data on the bus is simultaneously being shifted in; i2dat always contains the last data byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in i2dat. bit: 7 6 5 4 3 2 1 0 i2dat.7 i2dat.6 i2dat.5 i2dat.4 i2dat.3 i2dat.2 i2dat.1 i2dat.0 mnemonic: i2dat address: bch i2dat and the acknowledge bit form a 9-bit shift r egister, the acknowledge bit is controlled by the sio1 hardware and cannot be accessed by the cpu. serial data is shifted through the acknowledge bit into i2dat on the rising edges of serial clock pulses on the scl line. when a byte has been shifted into i2dat, the serial data is available in i2da t, and the acknowledge bit (ack or nack) is returned by the control logic during the ni nth clock pulse. serial data is sh ifted out from i2dat on the falling edges of scl clock pulses, and is shifted into i2dat on the rising edges of scl clock pulses. 26.2.3 the control register, i2con the cpu can read from and write to this 8-bit, direct ly addressable sfr. two bits are affected by the sio1 hardware: the si bit is set when a serial in terrupt is requested, and the sto bit is cleared when a stop condition is present on the bus. the sto bit is also cleared when ens1 = "0". bit: 7 6 5 4 3 2 1 0 - ens1 sta sto si aa - - mnemonic: i2con address: c0 bit name function 7 - reserved. 6 ens1 0: disable i2c serial function. the sda and scl output are in a high impedance state. sda and scl input signals are ignored, i2c is in the not addressed slave, and sto bit in i2con is forced to ?0?. no other bits are affected. p1.0 (scl) and p1.1 (sda) may be used as open drain i/o ports. 1: enable i2c serial function. the p1.0 and p1.1 port latches must be to logic 1.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 101 - revision a2 continued bit name function 5 sta the start flag. 0: the sta bit is reset, no start c ondition or repeated start condition will be generated. 1: the sta bit is set to enter a master mode, the i2c hardware checks the status o f i2c bus and generates a start condition if the bus is free. if bus is not free, then i2c waits for a stop condition and generates a start condition after a delay. if sta is set while i2c is already in a master mode and one or more bytes are transmitted or received, i2c transmits a repeated start condition. sta may be set any time. sta may also be set when i2c is an addressed slave. 4 sto the bit sto bit is set while i2c is in a master mode, a stop condition is transmitted to the i2c bus. when the stop condition is detected on the bus, the i2c hardware clears the sto flag. in a slave mode, the sto flag may be set to recover from an bus error condition. in this cases, no stop condition is transmitted to the i2c bus. however, the i2c hardware behaves as if a stop condition has been received and switches to the defined not addressed sl ave receiver mode. the sto flag is automatically cleared by hardware. if t he sta and sto bits are both set, then a stop condition is transmitted to the i2c bus if i2c is in a master mode (in a slave mode, i2c generates an internal stop condi tion which is not transmitted). i2c then transmits a start condition. 3 si 0: when the si flag is reset, no serial inte rrupt is requested, and there is no stretching on the serial clock on the scl line. 1: when a new sio1 state is present in t he s1status register, the si flag is set by hardware, and, if the ea and es bits (in ie r egister) are both set, a serial interrupt is requested. the only state that does not c ause si to be set is state f8h, which indicates that no relevant stat e information is available. when si is set, the low period of the serial clock on the scl line is stre tched, and the serial transfer is suspended. a high level on the scl line is unaffected by the serial interrupt flag. si must be cleared by software. 2 aa the assert acknowledge flag 0: a not acknowledge (high level to sda) will be returned during the acknowledge clock pulse on scl when: 1) a data has been received while sio1 is in the master receiver mode. 2) a data byte has been rece ived while sio1 is in the addressed slave receiver mode. 1: an acknowledge (low level to sda) will be returned during the acknowledge clock pulse on the scl line when: 1) the own slave address has been received. 2) a data byte has been received while sio1 is in the master receiver mode. 3) a data byte has been received while sio1 is in the addressed slave receiver mode. 1 - reserved. 0 - reserved.
w79e825/824/823a/822a/821a data sheet - 102 - 26.2.4 the i2c clock baud rate bits, i2clk the data baud rate of i2c is determines by i2clk regi ster when sio1 is in a master mode. it is not important when sio1 is in a slave mode. in the sl ave modes, sio1 will automatically synchronize with any clock frequency up to 400 khz from master i2c device. the data baud rate of i2c setting is data baud rate of i2c = fcpu / (i2clk+1). the fcpu=fosc/4. if fosc = 16mhz, the i2clk = 40(28h), so data baud rate of i2c = 16mhz /(4x (40 +1)) = 97.56kbits/sec. the block diagram is as below figure. bit: 7 6 5 4 3 2 1 0 i2clk.7 i2clk.6 i2clk.5 i2clk.4 i2clk.3 i2clk.2 i2clk.1 i2clk.0 mnemonic: i2clk address: beh bit name function 7 ~ 0 i2clk the i2c clock baud rate bits. 1 0 fosc 1/4 14-bits counter tif clear counter enti si div4 si to i2c interrupt i2c timer count block diagram 26.2.5 the status register, i2status i2status is an 8-bit read-only register. the three leas t significant bits are always 0. the five most significant bits contain the status code. there ar e 23 possible status codes. when i2status contains f8h, no serial interrupt is requested. all other i2status values correspond to defined sio1 states. when each of these states is entered, a status interrupt is requested (si = 1). a valid status code is present in i2status one machine cycle after si is set by hardware and is still present one machine cycle after si has been reset by software. in addition, state 00h stands for a bus error. a bu s error occurs when a start or stop condition is present at an illegal position in the format frame. examples of illegal positions are during the serial transfer of an address byte, a data byte or an acknowledge bit.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 103 - revision a2 26.3 operating modes of i2c the four operating modes are: master/transmi tter, master/receiver, slave/transmitter and slave/receiver. bits sta, sto and aa in i2con dec ide the next action the sio1 hardware will take after si is cleared. when the next action is comp leted, a new status code in i2status will be updated and si will be set by hardware in the same time . now, the interrupt service routine is entered (if the si interrupt is enabled), the new status code can be used to decide which appropriate service routine the software is to branch. data transfers in each mode ar e shown in the following figures. *** legend for the following four figures: 08h a start has been transmitted. (sta,sto,si,aa)=(0,0,0,x) sla+w will be transmitted; ack bit will be received. 18h sla+w has been transmitted; ack has been received. last state last action is done next setting in s1con expected next action next action is done new state software's access to s1dat with respect to "expected next actio n": software should load the data byte (to be transmitted) into s1dat before new s1con setting is done. (1) data byte will be transmitted: (2) sla+w (r) will be transmitted: software should load the sla+w/r (to be transmitted) into s1dat before new s1con setting is done. (3) data byte will be received: software can read the received data byte from s1dat while a new state is entered.
w79e825/824/823a/822a/821a data sheet - 104 - master transmitter mode 08h a start has been transmitted. (sta,sto,si,aa)=(0,0,0,x) sla+w will be transmitted; ack bit will be received. set sta to generate a start. 18h sla+w will be transmitted; ack bit will be received. or 20h sla+w will be transmitted; not ack bit will be received. (sta,sto,si,aa)=(1,0,0,x) a repeated start w ill be transmitted; (sta,sto,si,aa)=(0,0,0,x) data byte will be transmitted; ack will be received. (sta,sto,si,aa)=(0,1,0,x) a stop will be transmitted; sto flag will be reset. send a stop (sta,sto,si,aa)=(1,1,0,x) a stop followed by a start will be transmitted; sto flag will be reset. send a stop followed by a start 28h data byte in s1dat has been transmitted; ack has been received. or 30h data byte in s1dat has been transmitted; not ack has been received. 10h a repeated start has been transmitted. (sta,sto,si,aa)=(0,0,0,x) sla+r will be transmitted; ack bit will be transmitted; sio1 will be switched to mst/rec m ode. 38h arbitration lost in sla+r/w or data byte. (sta,sto,si,aa)=(0,0,0,x) i2c bus will be release; not address slv mode will be entered. (sta,sto,si,aa)=(1,0,0,x) a start will be transmitted when the bus becomes free. send a start when bus becomes free enter naslave from slave mode (c) to master/receiver (a) from master/receiver (b)
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 105 - revision a2 master receiver mode 08h a start has been transmitted. (sta,sto,si,aa)=(0,0,0,x) sla+r will be transmitted; ack bit will be received. set sta to generate a start. 40h sla+r has been transmitted; ack has been received. (sta,sto,si,aa)=(0,1,0,x) a stop will be transmitted; sto flag will be reset. (sta,sto,si,aa)=(1,1,0,x) a stop followed by a start will be transmitted; sto flag will be reset. (sta,sto,si,aa)=(0,0,0,0) data byte will be received; not ack will be returned. send a stop (sta,sto,si,aa)=(0,0,0,1) data byte will be received; ack will be returned. 10h a repeated start has been transmitted. (sta,sto,si,aa)=(0,0,0,x) sla+r will be transmitted; ack bit will be transmitted; sio1 will be switched to mst/rec mode. (sta,sto,si,aa)=(1,0,0,x) a start will be transmitted; when the bus becomes free (sta,sto,si,aa)=(0,0,0,x) i2c bus will be release; not address slv mode will be entered. enter naslave from master/transmitter (a) to master/transmitter (b) from slave mode (c) 48h sla+r has been transmitted; not ack has been received. 58h data byte has been received; not ack has been returned. 50h data byte has been received; ack has been returned. send a stop followed by a start 38h arbitration lost in not ack bit. send a start when bus becomes free (sta,sto,si,aa)=(1,0,0,x) a repeated start will be transmitted;
w79e825/824/823a/822a/821a data sheet - 106 - slave transmitter mode set aa a8h own sla+r has been received; ack has been return. or b0h arbitration lost sla+r/w as master; own sla+r has been received; ack has been return. (sta,sto,si,aa)=(1,0,0,1) switch to not address slv mode; own sla will be recognized; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(0,0,0,0) last data will be transmitted; ack will be received. (sta,sto,si,aa)=(0,0,0,1) data byte will be transmitted; ack will be received. send a start when bus becomes free c8h last data byte in s1dat has been transmitted; ack has been received. (sta,sto,si,aa)=(1,0,0,0) switch to not addressed slv mode; no recognition of own sla; a start will be transmitted when the becomes free. (sta,sto,si,aa)=(0,0,0,1) switch to not addressed slv mode; own sla will be recognized. (sta,sto,si,aa)=(0,0,0,0) switch to not addressed slv mode; no recognition of own sla. enter naslave to master mode (c) (sta,sto,si,aa)=(0,0,0,0) last data byte will be transmitted; ack will be received. (sta,sto,si,aa)=(0,0,0,1) data byte will be transmitted; ack will be received. c0h data byte or last data byte in s1dat has been transmitted; not ack has been received. b8h data byte in s1dat has been transmitted; ack has been received. a0h a stop or repeated start has been received while still addressed as slv/rec.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 107 - revision a2 slave receiver mode set aa 60h own sla+w has been received; ack has been return. or 68h arbitration lost sla+r/w as master; own sla+w has been received; ack has been return. (sta,sto,si,aa)=(1,0,0,1) switch to not address slv mode; own sla will be recognized; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(0,0,0,0) data will be received; not ack will be returned. (sta,sto,si,aa)=(0,0,0,1) data will be received; ack will be returned. send a start when bus becomes free 88h previously addressed with own sla address; not ack has been returned. (sta,sto,si,aa)=(1,0,0,0) switch to not addressed slv mode; no recognition of own sla; a start will be transmitted when the becomes free. (sta,sto,si,aa)=(0,0,0,1) switch to not addressed slv mode; own sla will be recognized. (sta,sto,si,aa)=(0,0,0,0) switch to not addressed slv mode; no recognition of own sla. enter naslave to master mode (c) (sta,sto,si,aa)=(0,0,0,0) data byte will be received; not ack will be returned. (sta,sto,si,aa)=(0,0,0,1) data byte will be received; ack will be returned. 80h previously addressed with own sla address; data has been received; ack has been returned. a0h a stop or repeated start has been received while still addressed as slv/rec.
w79e825/824/823a/822a/821a data sheet - 108 - gc mode set aa 70h reception of the general call address and one or more data bytes; ack has been return. or 78h arbitration lost sla+r/w as master; and address as sla by general call; ack has been return. (sta,sto,si,aa)=(1,0,0,1) switch to not address slv mode; own sla will be recognized; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(x,0,0,0) data will be received; not ack will be returned. (sta,sto,si,aa)=(x,0,0,1) data will be received; ack will be returned. send a start when bus becomes free 98h previously addressed with general call; data byte has been received; not ack has been returned. (sta,sto,si,aa)=(1,0,0,0) switch to not addressed slv mode; no recognition of own sla; a start will be transmitted when the becomes free. (sta,sto,si,aa)=(0,0,0,1) switch to not addressed slv mode; own sla will be recognized. (sta,sto,si,aa)=(0,0,0,0) switch to not addressed slv mode; no recognition of own sla. enter naslave to master mode (c) (sta,sto,si,aa)=(x,0,0,0) data byte will be received; not ack will be returned. (sta,sto,si,aa)=(x,0,0,1) data byte will be received; ack will be returned. 90h previously addressed with general call; data has been received; ack has been returned. a0h a stop or repeated start has been received while still addressed as slv/rec.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 109 - revision a2 27. icp(in-circuit program) flash program the contexts of flash in w79e82x series are empty by default. at the first use, you must program the flash eprom by external writer device or by icp(in-circuit program) tool. in the icp tool, the user must be taken icp?s program pins before design in system design board which pins in some application circuits are p1.5, p0.4 and p0.5, as below fi gure. in the icp program, the p1.5 must set to high voltage(~10.5v), and keeping this voltage to update code, data and/or configure two config bits. after finished, the hi gh voltage of p1.5 will be released. so when use icp program to suggest the power need power off then power on after icp program was finished on the system board. after entry icp program mode, all pin will be set to quasi-bidirectional mode, and output to level ?1?. the w79e82x series support progr am two flash eprom that are 16k/8k/4k/2k/1k bytes ap flash eprom and 256/128 bytes nvm data memory. this mode can separate update code or all update at ap flash eprom or nvm data memory if need. w79e82x chip p1.5 p0.4 p0.5 vdd vss to i/o pin to i/o pin to reset or input pin vss vdd vpp data clock vss icp program tool vcc jumper icp connector system board icp power jumper note: 1. when use icp to upgrade code, the p1.5, p0.4 and p0.5 must be taken within design system board. 2. after program finished by icp, to suggest system power must power off and remove icp connector then power on.
w79e825/824/823a/822a/821a data sheet - 110 - 28. config bits the w79e82x series have two config bits(confi g1, config2) that must be define at power up and can not be set the program after start of execut ion. those features are configured through the use of two flash eprom bytes, and the flash eprom can be programmed and verified repeatedly. until the code inside the flash eprom is confirmed ok, t he code can be protected. the protection of flash eprom (config2) and those operations on it are described below. the data of these bytes may be read by the movc instruction at the addresses. 28.1 config1 config register 1 config 1 : 76 54321 0 wdte: watchdog timer clock source bit. rpd: reset pin disable bit. config bit prhi: port reset high or low bit. bov: brownout voltage select bit. fosc1: cpu oscillator type select bit 1. fosc0: cpu oscillator type select bit 0. rpd wdte prhi bov - fosc0 fosc1 - - bit name function 7 wdte clock source of watchdog timer select bit: 0: the internal rc oscillator clock is for watchdog timer clock used. 1: the uc clock is for watchdog timer clock used. 6 rpd reset pin disable bit: 0: enable reset function of pin 1.5. 1: disable reset function of pin 1.5, and it to be used as an input port pin. 5 prhi port reset high or low bit: 0: port reset to low state. 1: port reset to high state. 4 bov brownout voltage select bit: 0: brownout detect voltage is 3.8v. 1: brownout detect voltage is 2.5v.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 111 - revision a2 continued bit name function 3 - reserved. 2 - reserved. 1 fosc1 cpu oscillator type select bit 1 0 fosc0 cpu oscillator type select bit 0 oscillator configuration bits: fosc1 fosc0 osc source 0 0 4mhz ~ 20mhz crystal 0 1 internal rc oscillator 1 0 reserved 1 1 external oscillator in xtal1 28.2 config2 config register 2 config 2 : 76 54321 0 c7: 16k/8k/4k/2k/1k flash eprom code lock bit. c6: 256/128 byte data lock bit. config bit c6 c7 - -- - - - c7: 16k/8k/4k/2k/1k flash eprom lock bit this bit is used to protect the customer's program code. it may be set after the programmer finishes the programming and verifies sequence. once this bi t is set to logic 0, both the flash eprom data and config registers can not be accessed again. c6: 256/128 byte data flash eprom lock bit this bit is used to protect the customer's data c ode. it may be set after the programmer finishes the programming and verifies sequence. once this bit is set to logic 0, both the data flash eprom and config registers can not be accessed again.
w79e825/824/823a/822a/821a data sheet - 112 - bit 7 bit 6 function description 1 1 both security of 16kb/8kb/4kb/2kb/1kb program code and 256/128 bytes data area are unlocked, those can be erased, programmed or read by writer or icp. 0 1 the 16kb/8kb/4kb/2kb/1kb program code area is locked, it can?t be read by writer or icp. 1 0 don?t support (invalid) 0 0 both security of 16kb/8kb/4kb/2kb/1kb program code and 256/128 bytes data area are locked, those can?t be read by write or icp.
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 113 - revision a2 29. the on-chip debugger with jtag interface the w79e82x series can support on-chip debugger that it is fully function debug for w79e825 , w79e824 , w79e823 , w79e822 and w79e821 , and provides the following functions: 1. eight breakpoints that detect the program counter 2. two enhanced watch breakpoints that can hold the program by observing cpu access to data memory and flash eprom 3. ability to read and write data memory while the program is held 4. ability to write application code to the flash eprom 30. absolute maximum ratings symbol parameter condition rating unit dc power supply vdd ? vss -0.3 +7.0 v input voltage vin vss-0.3 vdd+0.3 v operating temperature ta -40 +85 c storage temperature tst -55 +150 c note: exposure to conditions beyond those list ed under absolute maximum ratings may adversely affects the lift and reliability of the device.
w79e825/824/823a/822a/821a data sheet - 114 - 31. dc electrical characteristics (ta = -40~85 c, unless otherwise specified.) specification parameter symbol min. max. unit test conditions operating voltage vdd 2.7 5.5 v vdd=4.5v ~ 5.5v @ 20mhz vdd=2.7v ~ 5.5v @ 12mhz - 25 ma no load, rst = vss,vdd = 5.0v operating current idd - 7 ma no load, rst = vss, vdd= 3.0v - 20 ma no load, vdd = 5.5v idle current iidle - 12 ma no load, vdd = 3.0v - 10 a no load, vdd = 5.5v power down current ipwdn - 10 ua no load, vdd = 3.0v input current p0, p1, p2 iin1 -50 +10 a vdd = 5.5v, 0 w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 115 - revision a2 dc electrical characteristics, continued specification parameter symbol min. max. unit test conditions - 1.0 v vdd = 2.7v, iol = 20 ma output low voltage p0, p1, p2 (push-pull mode) vol1 - 0.4 v vdd = 2.7v, iol = 3.2 ma output high voltage p0, p1, p2 (push-pull mode) voh vdd- 0.7 - v vdd = 2.7v, ioh = -1ma brownout voltage with bov=1 v bo2.5 2.45 2.65 v ta = -0 to 70 c brownout voltage with bov=0 v bo3.8 3.45 3.90 v ta = -0 to 70 c comparator reference voltage vref 1.11 1.41 v notes: *1. rst pin is a schmitt trigger input. *2. xtal1 is a cmos input. *3. pins of p0, p1,p2 can source a transition current when they are being externally driven from 1 to 0. the transit ion current reaches its maximum value when vin approximates to 2v. 31.1 the adc converter dc electrical characteristics (vdd ? vss = 3.0~5v, ta = -40~85 c, fosc = 20mhz, unless otherwise specified.) specification parameter symbol min. max. unit test conditions analog input avin vss-0.2 vdd+0.2 v analog input capacitance ci - 15 pf adc clock adcclk 200khz 5mhz hz adc circuit input clock conversion time t c 50t clcl us differential non-linearity dnl -1 +1 lsb integral non-linearity inl -2 +2 lsb offset error ofe -2 +2 lsb gain error ge -1 +1 % absolute voltage error ae -1 +1 lsb channel to channel matching ctcm -1 +1 lsb crosstalk between inputs of port 1 cro -60 db 0~100khz
w79e825/824/823a/822a/821a data sheet - 116 - 31.2 the comparator electrical characteristics (vdd ? vss = 3.0~5v, ta = -40~85 c, fosc = 20mhz, unless otherwise specified.) specification parameter symbol min. max. unit test conditions offset voltage comparator input v io -10 10 mv common mode range comparator inputs v cr 0 vdd-0.3 v common mode rejection ratio cmrr -50 db response time t rs 500 ns comparator enable to output valid time t en 10 us input leakage current, comparator i il -10 10 ua 0< v in w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 117 - revision a2 34. ac specification parameter symbol variable clock min. variable clock max. units oscillator frequency 1/t clcl 0 20 mhz 35. typical application circuits crystal c1 c2 r 4mhz ~ 20 mhz without without without the above table shows the reference values for crystal applications. xtal2 xtal1 w79e825 w79e824 c1 c2 r
w79e825/824/823a/822a/821a data sheet - 118 - 36. package dimensions 36.1 20-pin so 20l sop-300mil l o c e h a1 a e b d seating plane y 0.25 gauge plane e 1 20 11 10 7.60 0.32 0.51 0.30 e c b a1 7.40 0.23 0.33 0.10 0.299 0.013 0.020 0.012 0.291 0.009 0.013 0.004 max. dimension in mm 2.65 a symbol min. 2.35 dimension in inch 0.104 min. 0.093 max. control demensions are in milmeters . 1.27 0.10 10.65 l y h 08 0.40 10.00 e 1.27 bsc 0.050 0.004 0.419 0 0.016 0.394 8 0.050 bsc e d 12.60 13.00 0.496 0.512
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 119 - revision a2 36.2 20-pin dip 20l pdip 300mil 1.63 1.47 0.064 0.058 symbol min nom max max nom min dimension in inch dimension in mm a b c d e a l s a a 1 2 e 0.060 1.52 0.175 4.45 0.010 0.125 0.016 0.130 0.018 0.135 0.022 3.18 0.41 0.25 3.30 0.46 3.43 0.56 0.008 0.120 0.375 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.255 0.250 0.245 6.48 6.35 6.22 9.53 7.62 7.37 7.87 0.300 0.290 0.310 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 1.026 1.040 20.06 26.42 015 0.075 1.91 0.355 0.335 8.51 9.02 15 0 seating plane a e 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 20 110 11
w79e825/824/823a/822a/821a data sheet - 120 - 36.3 24-pin so 24l sop-300mil l o c e h a1 a e b d seating plane y 0.25 gauge plane e 1 24 13 12 7.60 0.32 0.51 0.30 e c b a1 7.40 0.23 0.33 0.10 0.299 0.013 0.020 0.012 0.291 0.009 0.013 0.004 max. dimension in mm 2.65 a symbol min. 2.35 dimension in inch 0.104 min. 0.093 max. control demensions are in milmeters . 1.27 0.10 10.65 l y h 08 0.40 10.00 e 1.27 bsc 0.050 0.004 0.419 0 0.016 0.394 8 0.050 bsc e d 15.20 15.60 0.598 0.614
w79e825/824/823a/822a/821a data sheet publication release date: may 03, 2006 - 121 - revision a2 37. revision history version date page description a1 mar. 30, 2006 - initial issued a2 may 03, 2006 to add w79e823/822/821 parts and function description important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

▲Up To Search▲

Price & Availability of W79E825ASN

	To Download W79E825ASN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .